[llvm][ARM][NFC] Renaming FeaturePrefLoopLogAlign #109932
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The feature 'FeaturePrefLoopLogAlign' was misleading as it was used to set the alignment of branch instructions such as functions. Renamed to FeaturePrefBranchInstAlignment. Change-Id: I88edcf2fe946d50fc33765273d36e1abcbe9d959
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@llvm/pr-subscribers-backend-arm Author: Nashe Mncube (nasherm) ChangesThe feature 'FeaturePrefLoopLogAlign' was misleading as it was used to set the alignment of branch instructions such as functions. Renamed to FeaturePrefBranchInstAlignment. Full diff: https://github.com/llvm/llvm-project/pull/109932.diff 5 Files Affected:
diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
index dc0e86c696f63a..d40da67a7f2ba5 100644
--- a/llvm/lib/Target/ARM/ARMFeatures.td
+++ b/llvm/lib/Target/ARM/ARMFeatures.td
@@ -372,11 +372,11 @@ def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Prefers32BitThumb", "true",
"Prefer 32-bit Thumb instrs">;
-def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopLogAlignment","2",
- "Prefer 32-bit alignment for loops">;
+def FeaturePrefBranchInstAlign32 : SubtargetFeature<"loop-align", "PrefBranchInstLogAlignment","2",
+ "Prefer 32-bit alignment for branch instructions (loops, functions)">;
-def FeaturePrefLoopAlign64 : SubtargetFeature<"loop-align-64", "PrefLoopLogAlignment","3",
- "Prefer 64-bit alignment for loops">;
+def FeaturePrefBranchInstAlign64 : SubtargetFeature<"loop-align-64", "PrefBranchInstLogAlignment","3",
+ "Prefer 64-bit alignment for branch instructions (loops, functions">;
def FeatureMVEVectorCostFactor1 : SubtargetFeature<"mve1beat", "MVEVectorCostFactor", "4",
"Model MVE instructions as a 1 beat per tick architecture">;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index a03928b618df03..d3c027c999b7b3 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1635,8 +1635,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
// Prefer likely predicted branches to selects on out-of-order cores.
PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
- setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
- setPrefFunctionAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
+ setPrefLoopAlignment(
+ Align(1ULL << Subtarget->getPrefBranchInstLogAlignment()));
+ setPrefFunctionAlignment(
+ Align(1ULL << Subtarget->getPrefBranchInstLogAlignment()));
setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
}
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
index a66a2c0b1981d8..0f803af81eead3 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -324,7 +324,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m,
ProcM3,
- FeaturePrefLoopAlign32,
+ FeaturePrefBranchInstAlign32,
FeatureUseMISched,
FeatureHasNoBranchPredictor]>;
@@ -335,7 +335,7 @@ def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m,
def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
FeatureVFP4_D16_SP,
- FeaturePrefLoopAlign32,
+ FeaturePrefBranchInstAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
@@ -344,7 +344,7 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em,
ProcM7,
FeatureFPARMv8_D16,
- FeaturePrefLoopAlign64,
+ FeaturePrefBranchInstAlign64,
FeatureUseMIPipeliner,
FeatureUseMISched]>;
@@ -355,7 +355,7 @@ def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
- FeaturePrefLoopAlign32,
+ FeaturePrefBranchInstAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
@@ -365,7 +365,7 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
- FeaturePrefLoopAlign32,
+ FeaturePrefBranchInstAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
@@ -377,7 +377,7 @@ def : ProcessorModel<"cortex-m55", CortexM55Model, [ARMv81mMainline,
FeatureFPARMv8_D16,
FeatureUseMISched,
FeatureHasNoBranchPredictor,
- FeaturePrefLoopAlign32,
+ FeaturePrefBranchInstAlign32,
FeatureHasSlowFPVMLx,
HasMVEFloatOps,
FeatureFixCMSE_CVE_2021_35465]>;
@@ -386,7 +386,7 @@ def : ProcessorModel<"cortex-m85", CortexM85Model, [ARMv81mMainline,
FeatureDSP,
FeatureFPARMv8_D16,
FeaturePACBTI,
- FeaturePrefLoopAlign64,
+ FeaturePrefBranchInstAlign64,
FeatureUseMISched,
HasMVEFloatOps]>;
@@ -396,7 +396,7 @@ def : ProcessorModel<"cortex-m52", CortexM55Model, [ARMv81mMainline,
FeatureHasNoBranchPredictor,
FeaturePACBTI,
FeatureUseMISched,
- FeaturePrefLoopAlign32,
+ FeaturePrefBranchInstAlign32,
FeatureHasSlowFPVMLx,
FeatureMVEVectorCostFactor1,
HasMVEFloatOps]>;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 13018e647e8223..fcd77bbf293726 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -302,7 +302,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
LdStMultipleTiming = SingleIssuePlusExtras;
MaxInterleaveFactor = 4;
if (!isThumb())
- PrefLoopLogAlignment = 3;
+ PrefBranchInstLogAlignment = 3;
break;
case Kryo:
break;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index fa20f4b590bea5..02c5ced6d30475 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -133,7 +133,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
int PreISelOperandLatencyAdjustment = 2;
/// What alignment is preferred for loop bodies and functions, in log2(bytes).
- unsigned PrefLoopLogAlignment = 0;
+ unsigned PrefBranchInstLogAlignment = 0;
/// The cost factor for MVE instructions, representing the multiple beats an
// instruction can take. The default is 2, (set in initSubtargetFeatures so
@@ -476,7 +476,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
return isROPI() || !isTargetELF();
}
- unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
+ unsigned getPrefBranchInstLogAlignment() const {
+ return PrefBranchInstLogAlignment;
+ }
unsigned
getMVEVectorCostFactor(TargetTransformInfo::TargetCostKind CostKind) const {
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davemgreen
approved these changes
Sep 25, 2024
Change-Id: If0549d2bd62209279f5d21b90609ad42a1d116d4
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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Personally I would just kept it consistent with the subtarget feature spelling, e.g. FeatureLoopAlign to match loop-align. But I don't feel that strongly. If you're going to stick with the current suggestion then maybe expand "Pref" to "Prefer" since it only saves two characters.
I've renamed |
Change-Id: Ibf1ffab27184a12a5d0fdab2ec7af437192552b5
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Unfortunately you can't do that; it will break any existing IR that refers to this subtarget feature as |
Ah I see, thanks for pointing this out. |
Sterling-Augustine
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Sep 27, 2024
The feature 'FeaturePrefLoopAlignment' was misleading as it was used to set the alignment of branch targets such as functions. Renamed to FeaturePreferfBranchAlignment.
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The feature 'FeaturePrefLoopLogAlign' was misleading as it was used to set the alignment of branch instructions such as functions. Renamed to FeaturePrefBranchInstAlignment.