[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU #110085

AlbertHuang-CPU · 2024-09-26T07:30:13Z

STAR-MC1 is an Armv8m CPU.

Technical specifications available at:
https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160

github-actions · 2024-09-26T07:30:36Z

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llvmbot · 2024-09-26T07:31:10Z

@llvm/pr-subscribers-clang-driver
@llvm/pr-subscribers-clang

@llvm/pr-subscribers-backend-arm

Author: Albert Huang (AlbertHuang-CPU)

Changes

STAR-MC1 is an Armv8m CPU.

Technical specifications available at:
https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160

Full diff: https://github.com/llvm/llvm-project/pull/110085.diff

4 Files Affected:

(modified) llvm/include/llvm/TargetParser/ARMTargetParser.def (+1)
(modified) llvm/lib/Target/ARM/ARMProcessors.td (+10)
(modified) llvm/lib/TargetParser/Host.cpp (+6)
(modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+4-1)

diff --git a/llvm/include/llvm/TargetParser/ARMTargetParser.def b/llvm/include/llvm/TargetParser/ARMTargetParser.def
index e5a1ce54fd46a7..95dc24931e00c0 100644
--- a/llvm/include/llvm/TargetParser/ARMTargetParser.def
+++ b/llvm/include/llvm/TargetParser/ARMTargetParser.def
@@ -337,6 +337,7 @@ ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m7", ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m23", ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
+ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
 ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
 ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
              (ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
diff --git a/llvm/lib/Target/ARM/ARMProcessors.td b/llvm/lib/Target/ARM/ARMProcessors.td
index a66a2c0b1981d8..293f1fabda7b4c 100644
--- a/llvm/lib/Target/ARM/ARMProcessors.td
+++ b/llvm/lib/Target/ARM/ARMProcessors.td
@@ -362,6 +362,16 @@ def : ProcessorModel<"cortex-m33", CortexM4Model,       [ARMv8mMainline,
                                                          FeatureHasNoBranchPredictor,
                                                          FeatureFixCMSE_CVE_2021_35465]>;
 
+def : ProcessorModel<"star-mc1", CortexM4Model,         [ARMv8mMainline,
+                                                         FeatureDSP,
+                                                         FeatureFPARMv8_D16_SP,
+                                                         FeaturePrefLoopAlign32,
+                                                         FeatureHasSlowFPVMLx,
+                                                         FeatureHasSlowFPVFMx,
+                                                         FeatureUseMISched,
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeatureFixCMSE_CVE_2021_35465]>;
+
 def : ProcessorModel<"cortex-m35p", CortexM4Model,      [ARMv8mMainline,
                                                          FeatureDSP,
                                                          FeatureFPARMv8_D16_SP,
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 616e4eda1dd29d..1500c71f4039b5 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -342,6 +342,12 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
     }
   }
 
+  if (Implementer == "0x63") { // Arm China.
+    return StringSwitch<const char *>(Part)
+        .Case("0x132", "star-mc1")
+        .Default("generic");
+  }
+
   if (Implementer == "0x6d") { // Microsoft Corporation.
     // The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
     return StringSwitch<const char *>(Part)
diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp
index 13db80ab5c68ea..7b86290a71ee4a 100644
--- a/llvm/unittests/TargetParser/TargetParserTest.cpp
+++ b/llvm/unittests/TargetParser/TargetParserTest.cpp
@@ -490,6 +490,9 @@ INSTANTIATE_TEST_SUITE_P(
         ARMCPUTestParams<uint64_t>("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
                                    ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
                                    "8-M.Mainline"),
+        ARMCPUTestParams<uint64_t>("star-mc1", "armv8-m.main", "fpv5-sp-d16",
+                                   ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                                   "8-M.Mainline"),
         ARMCPUTestParams<uint64_t>("cortex-m35p", "armv8-m.main", "fpv5-sp-d16",
                                    ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
                                    "8-M.Mainline"),
@@ -518,7 +521,7 @@ INSTANTIATE_TEST_SUITE_P(
                                    "7-S")),
     ARMCPUTestParams<uint64_t>::PrintToStringParamName);
 
-static constexpr unsigned NumARMCPUArchs = 92;
+static constexpr unsigned NumARMCPUArchs = 93;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector<StringRef, NumARMCPUArchs> List;

davemgreen

As far as I can see this LGTM. Good to see the addition.

Are you happy for the patch to be committed?

jthackray

Thanks Albert. I think you might need to also update target-invalid-cpu-note/arm.c as well?

jthackray

Could you add star-mc1 to clang/test/Driver/arm-cortex-cpus-2.c?

jthackray · 2024-09-26T10:16:26Z

llvm/lib/Target/ARM/ARMProcessors.td

+                                                         FeatureHasSlowFPVFMx,
+                                                         FeatureUseMISched,
+                                                         FeatureHasNoBranchPredictor,
+                                                         FeatureFixCMSE_CVE_2021_35465]>;


Could you add the following to llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll:

; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -verify-machineinstrs | \ ; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465 ; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -mattr=-fpregs -verify-machineinstrs | \ ; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465

Thanks Jonathan. The two files updated and the changes passed the Unit tests of clang and llvm.

jthackray

Thanks, LGTM.

davemgreen · 2024-10-01T08:49:49Z

Can you rebase? FeaturePrefLoopAlign32 has been renamed. Then if you are happy for this to be committed then let us know and we can hit the squash and merge button (it is not always obvious who does and does not have commit access).

AlbertHuang-CPU · 2024-10-14T11:17:42Z

Hi David, rebase done. Could you help to merge?

jthackray · 2024-10-14T12:48:59Z

Hi David, rebase done. Could you help to merge?

It doesn't look like it builds at the moment. Happy to help merge when it's ready :)

davemgreen · 2024-10-14T14:48:20Z

Hi David, rebase done. Could you help to merge?

Thanks - it looks like the errors were unrelated - something that was broken on trunk earlier. Please yell if it does look like something is going wrong.

github-actions · 2024-10-14T14:48:32Z

@AlbertHuang-CPU Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

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STAR-MC1 is an Armv8m CPU. Technical specifications available at: https://www.armchina.com/download/Documents/Application-Notes/Technical-Reference-Manual?infoId=160

llvmbot added the backend:ARM label Sep 26, 2024

davemgreen requested review from jthackray and davemgreen September 26, 2024 08:12

davemgreen approved these changes Sep 26, 2024

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jthackray reviewed Sep 26, 2024

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llvmbot added the clang Clang issues not falling into any other category label Sep 26, 2024

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llvmbot added the clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' label Sep 26, 2024

jthackray approved these changes Sep 26, 2024

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AlbertHuang-CPU force-pushed the toAdd_star-mc1 branch from 092cd26 to 0730b00 Compare October 14, 2024 11:14

AlbertHuang-CPU added 4 commits October 14, 2024 19:15

[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU

feae352

amending for review comment

dade3b8

more changes for the tests

43025c1

update FeaturePreLoopAlign32 as the name changed

22a187a

AlbertHuang-CPU force-pushed the toAdd_star-mc1 branch from 0730b00 to 22a187a Compare October 14, 2024 11:15

davemgreen merged commit aa2c0f3 into llvm:main Oct 14, 2024
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