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[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU #110085

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Merged
merged 4 commits into from
Oct 14, 2024
Merged

[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU #110085

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feae352
[ARM] [AArch32] Add support for Arm China STAR-MC1 CPU
AlbertHuang-CPU Sep 26, 2024
dade3b8
amending for review comment
AlbertHuang-CPU Sep 26, 2024
43025c1
more changes for the tests
AlbertHuang-CPU Sep 26, 2024
22a187a
update FeaturePreLoopAlign32 as the name changed
AlbertHuang-CPU Oct 14, 2024
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2 changes: 2 additions & 0 deletions clang/test/Driver/arm-cortex-cpus-2.c
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Expand Up @@ -559,8 +559,10 @@
// CHECK-CPUV8MBASE: "-cc1"{{.*}} "-triple" "thumbv8m.base-

// RUN: %clang -target arm -mcpu=cortex-m33 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M33 %s
// RUN: %clang -target arm -mcpu=star-mc1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-STAR-MC1 %s
// RUN: %clang -target arm -mcpu=cortex-m35p -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M35P %s
// CHECK-CORTEX-M33: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "cortex-m33"
// CHECK-STAR-MC1: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "star-mc1"
// CHECK-CORTEX-M35P: "-cc1"{{.*}} "-triple" "thumbv8m.main-{{.*}} "-target-cpu" "cortex-m35p"

// RUN: %clang -target arm -mcpu=cortex-m55 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CORTEX-M55 %s
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1 change: 1 addition & 0 deletions clang/test/Misc/target-invalid-cpu-note/arm.c
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Expand Up @@ -65,6 +65,7 @@
// CHECK-SAME: {{^}}, cortex-m7
// CHECK-SAME: {{^}}, cortex-m23
// CHECK-SAME: {{^}}, cortex-m33
// CHECK-SAME: {{^}}, star-mc1
// CHECK-SAME: {{^}}, cortex-m35p
// CHECK-SAME: {{^}}, cortex-m55
// CHECK-SAME: {{^}}, cortex-m85
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1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/ARMTargetParser.def
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Expand Up @@ -342,6 +342,7 @@ ARM_CPU_NAME("cortex-m4", ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m7", ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m23", ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
ARM_CPU_NAME("cortex-m33", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("star-mc1", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m35p", ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
ARM_CPU_NAME("cortex-m55", ARMV8_1MMainline, FK_FP_ARMV8_FULLFP16_D16, false,
(ARM::AEK_DSP | ARM::AEK_SIMD | ARM::AEK_FP | ARM::AEK_FP16))
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10 changes: 10 additions & 0 deletions llvm/lib/Target/ARM/ARMProcessors.td
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Expand Up @@ -362,6 +362,16 @@ def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline,
FeatureHasNoBranchPredictor,
FeatureFixCMSE_CVE_2021_35465]>;

def : ProcessorModel<"star-mc1", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
FeaturePreferBranchAlign32,
FeatureHasSlowFPVMLx,
FeatureHasSlowFPVFMx,
FeatureUseMISched,
FeatureHasNoBranchPredictor,
FeatureFixCMSE_CVE_2021_35465]>;
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Could you add the following to llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll:

; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -verify-machineinstrs | \
; RUN:   FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465

; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -mattr=-fpregs -verify-machineinstrs | \
; RUN:   FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465

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Thanks Jonathan. The two files updated and the changes passed the Unit tests of clang and llvm.


def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline,
FeatureDSP,
FeatureFPARMv8_D16_SP,
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6 changes: 6 additions & 0 deletions llvm/lib/TargetParser/Host.cpp
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Expand Up @@ -342,6 +342,12 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
}
}

if (Implementer == "0x63") { // Arm China.
return StringSwitch<const char *>(Part)
.Case("0x132", "star-mc1")
.Default("generic");
}

if (Implementer == "0x6d") { // Microsoft Corporation.
// The Microsoft Azure Cobalt 100 CPU is handled as a Neoverse N2.
return StringSwitch<const char *>(Part)
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6 changes: 6 additions & 0 deletions llvm/test/CodeGen/ARM/cmse-cve-2021-35465.ll
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Expand Up @@ -7,6 +7,9 @@
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 -verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
;
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
;
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p -verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-FP-CVE-2021-35465
;
Expand All @@ -17,6 +20,9 @@
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m33 -mattr=-fpregs -verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
;
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=star-mc1 -mattr=-fpregs -verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
;
; RUN: llc %s -o - -mtriple=thumbv8m.main -mcpu=cortex-m35p -mattr=-fpregs -verify-machineinstrs | \
; RUN: FileCheck %s --check-prefix=CHECK-8M-NOFP-CVE-2021-35465
;
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5 changes: 4 additions & 1 deletion llvm/unittests/TargetParser/TargetParserTest.cpp
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Expand Up @@ -490,6 +490,9 @@ INSTANTIATE_TEST_SUITE_P(
ARMCPUTestParams<uint64_t>("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-M.Mainline"),
ARMCPUTestParams<uint64_t>("star-mc1", "armv8-m.main", "fpv5-sp-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-M.Mainline"),
ARMCPUTestParams<uint64_t>("cortex-m35p", "armv8-m.main", "fpv5-sp-d16",
ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
"8-M.Mainline"),
Expand Down Expand Up @@ -518,7 +521,7 @@ INSTANTIATE_TEST_SUITE_P(
"7-S")),
ARMCPUTestParams<uint64_t>::PrintToStringParamName);

static constexpr unsigned NumARMCPUArchs = 92;
static constexpr unsigned NumARMCPUArchs = 93;

TEST(TargetParserTest, testARMCPUArchList) {
SmallVector<StringRef, NumARMCPUArchs> List;
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