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[TableGen] [NFC] Refine TableGen code to comply with clang-tidy checks #113318

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Merged
merged 3 commits into from
Oct 29, 2024
Merged

[TableGen] [NFC] Refine TableGen code to comply with clang-tidy checks #113318

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25c6670
refine TableGen files to comply with clang-tidy checks
jerryyiransun Oct 21, 2024
2d70629
change Arm to ARM in function declarition
jerryyiransun Oct 28, 2024
3d7eccc
Merge branch 'main' into jerryyiransun/TableGen-style-fix
arsenm Oct 29, 2024
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20 changes: 10 additions & 10 deletions llvm/utils/TableGen/ARMTargetDefEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -25,19 +25,19 @@
using namespace llvm;

/// Collect the full set of implied features for a SubtargetFeature.
static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
const Record *Rec) {
assert(Rec->isSubClassOf("SubtargetFeature") &&
"Rec is not a SubtargetFeature");

SeenFeats.insert(Rec);
for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
CollectImpliedFeatures(SeenFeats, Implied);
collectImpliedFeatures(SeenFeats, Implied);
}

static void CheckFeatureTree(const Record *Root) {
static void checkFeatureTree(const Record *Root) {
std::set<const Record *> SeenFeats;
CollectImpliedFeatures(SeenFeats, Root);
collectImpliedFeatures(SeenFeats, Root);

// Check that each of the mandatory (implied) features which is an
// ExtensionWithMArch is also enabled by default.
Expand All @@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
}
}

static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
static void emitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";

// Look through all SubtargetFeature defs with the given FieldName, and
// collect the set of all Values that that FieldName is set to.
auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
llvm::StringSet<> Set;
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
if (Rec->getValueAsString("FieldName") == FieldName) {
Expand Down Expand Up @@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
<< "#endif\n\n";
const StringSet<> ARMProcFamilyVals =
gatherSubtargetFeatureFieldValues("ARMProcFamily");
GatherSubtargetFeatureFieldValues("ARMProcFamily");
for (const StringRef &Family : ARMProcFamilyVals.keys())
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
Expand All @@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_ARCHITECTURE(ENUM)\n"
<< "#endif\n\n";
// This should correspond to instances of the Architecture tablegen class.
const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
for (const StringRef &Arch : ARMArchVals.keys())
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
OS << "\n#undef ARM_ARCHITECTURE\n\n";
Expand Down Expand Up @@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);

CheckFeatureTree(Arch);
checkFeatureTree(Arch);

OS << " {\n"
<< " \"" << Name << "\",\n"
Expand Down Expand Up @@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
}

static TableGen::Emitter::Opt
X("gen-arm-target-def", EmitARMTargetDef,
X("gen-arm-target-def", emitARMTargetDef,
"Generate the ARM or AArch64 Architecture information header.");
48 changes: 24 additions & 24 deletions llvm/utils/TableGen/CallingConvEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -35,12 +35,12 @@ class CallingConvEmitter {
public:
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}

void run(raw_ostream &o);
void run(raw_ostream &O);
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nit: can this be OS. I've seen that as commonly used variable name for raw_ostream?

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Do you want me to change all &O to &OS in the file? There are quite a few methods in this file that have raw_ostream as parameter and they are all defined to be &O

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Yes, since you are changing the, you might as well use the preferred name

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@jurahul should I create a new PR for this change? It looks like there are few other files that also needs this modification. I think it might introduce too many changed files in this PR.


private:
void EmitCallingConv(const Record *CC, raw_ostream &O);
void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
void EmitArgRegisterLists(raw_ostream &O);
void emitCallingConv(const Record *CC, raw_ostream &O);
void emitAction(const Record *Action, indent Indent, raw_ostream &O);
void emitArgRegisterLists(raw_ostream &O);
};
} // End anonymous namespace

Expand Down Expand Up @@ -75,16 +75,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
Records.getTimer().startTimer("Emit full descriptions");
for (const Record *CC : CCs) {
if (!CC->getValueAsBit("Custom")) {
EmitCallingConv(CC, O);
emitCallingConv(CC, O);
}
}

EmitArgRegisterLists(O);
emitArgRegisterLists(O);

O << "\n#endif // CC_REGISTER_LIST\n";
}

void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
const ListInit *CCActions = CC->getValueAsListInit("Actions");
Counter = 0;

Expand All @@ -107,8 +107,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
<< std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
// Emit all of the actions, in order.
for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
const Record *Action = CCActions->getElementAsRecord(i);
for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
const Record *Action = CCActions->getElementAsRecord(I);
SwiftAction =
llvm::any_of(Action->getSuperClasses(),
[](const std::pair<const Record *, SMRange> &Class) {
Expand All @@ -117,23 +117,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
});

O << "\n";
EmitAction(Action, indent(2), O);
emitAction(Action, indent(2), O);
}

O << "\n return true; // CC didn't match.\n";
O << "}\n";
}

void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
raw_ostream &O) {
if (Action->isSubClassOf("CCPredicateAction")) {
O << Indent << "if (";

if (Action->isSubClassOf("CCIfType")) {
const ListInit *VTs = Action->getValueAsListInit("VTs");
for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
const Record *VT = VTs->getElementAsRecord(i);
if (i != 0)
for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
const Record *VT = VTs->getElementAsRecord(I);
if (I != 0)
O << " ||\n " << Indent;
O << "LocVT == " << getEnumName(getValueType(VT));
}
Expand All @@ -146,7 +146,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}

O << ") {\n";
EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
O << Indent << "}\n";
} else {
if (Action->isSubClassOf("CCDelegateTo")) {
Expand All @@ -171,8 +171,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
if (SwiftAction)
AssignedSwiftRegsMap[CurrentAction].insert(Name);
else
Expand Down Expand Up @@ -230,16 +230,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
for (unsigned i = 0, e = RegList->size(); i != e; ++i)
O << LS << getQualifiedName(RegList->getElementAsRecord(i));
for (unsigned I = 0, E = RegList->size(); I != E; ++I)
O << LS << getQualifiedName(RegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";

O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
<< "[] = {\n";
O << Indent << " ";
ListSeparator LSS;
for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";

O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
Expand Down Expand Up @@ -287,8 +287,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< ShadowRegListNumber << "[] = {\n";
O << Indent << " ";
ListSeparator LS;
for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";

O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
Expand Down Expand Up @@ -357,7 +357,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
}

void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
// Transitively merge all delegated CCs into AssignedRegsMap.
using EntryTy = std::pair<std::string, std::set<std::string>>;
bool Redo;
Expand Down
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