[TableGen] [NFC] Refine TableGen code to comply with clang-tidy checks
#113318
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llvmbot
added
backend:RISC-V
tablegen
llvm:globalisel
backend:DirectX
llvm:SelectionDAG
|
@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-llvm-selectiondag Author: Jerry Sun (jerryyiransun) ChangesPatch is 124.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113318.diff 23 Files Affected:
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 6b8ebf96cdf383..fe8a82e6d7e617 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -25,19 +25,19 @@
using namespace llvm;
/// Collect the full set of implied features for a SubtargetFeature.
-static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
+static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
const Record *Rec) {
assert(Rec->isSubClassOf("SubtargetFeature") &&
"Rec is not a SubtargetFeature");
SeenFeats.insert(Rec);
for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
- CollectImpliedFeatures(SeenFeats, Implied);
+ collectImpliedFeatures(SeenFeats, Implied);
}
-static void CheckFeatureTree(const Record *Root) {
+static void checkFeatureTree(const Record *Root) {
std::set<const Record *> SeenFeats;
- CollectImpliedFeatures(SeenFeats, Root);
+ collectImpliedFeatures(SeenFeats, Root);
// Check that each of the mandatory (implied) features which is an
// ExtensionWithMArch is also enabled by default.
@@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
}
}
-static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
// Look through all SubtargetFeature defs with the given FieldName, and
// collect the set of all Values that that FieldName is set to.
- auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+ auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
llvm::StringSet<> Set;
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
if (Rec->getValueAsString("FieldName") == FieldName) {
@@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
<< "#endif\n\n";
const StringSet<> ARMProcFamilyVals =
- gatherSubtargetFeatureFieldValues("ARMProcFamily");
+ GatherSubtargetFeatureFieldValues("ARMProcFamily");
for (const StringRef &Family : ARMProcFamilyVals.keys())
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
@@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_ARCHITECTURE(ENUM)\n"
<< "#endif\n\n";
// This should correspond to instances of the Architecture tablegen class.
- const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+ const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
for (const StringRef &Arch : ARMArchVals.keys())
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
OS << "\n#undef ARM_ARCHITECTURE\n\n";
@@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- CheckFeatureTree(Arch);
+ checkFeatureTree(Arch);
OS << " {\n"
<< " \"" << Name << "\",\n"
@@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
}
static TableGen::Emitter::Opt
- X("gen-arm-target-def", EmitARMTargetDef,
+ X("gen-arm-target-def", emitArmTargetDef,
"Generate the ARM or AArch64 Architecture information header.");
diff --git a/llvm/utils/TableGen/Attributes.cpp b/llvm/utils/TableGen/Attributes.cpp
index ed00debc398cb9..652dd31a9adb27 100644
--- a/llvm/utils/TableGen/Attributes.cpp
+++ b/llvm/utils/TableGen/Attributes.cpp
@@ -9,7 +9,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
-#include <vector>
using namespace llvm;
#define DEBUG_TYPE "attr-enum"
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index 3718486ff7ad4e..8c347456eb8940 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -17,7 +17,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
-#include <algorithm>
#include <vector>
using namespace llvm;
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index fefc407c354a5d..e44b13f0436313 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -34,12 +34,12 @@ class CallingConvEmitter {
public:
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- void EmitCallingConv(const Record *CC, raw_ostream &O);
- void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
- void EmitArgRegisterLists(raw_ostream &O);
+ void emitCallingConv(const Record *CC, raw_ostream &O);
+ void emitAction(const Record *Action, indent Indent, raw_ostream &O);
+ void emitArgRegisterLists(raw_ostream &O);
};
} // End anonymous namespace
@@ -74,16 +74,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
Records.startTimer("Emit full descriptions");
for (const Record *CC : CCs) {
if (!CC->getValueAsBit("Custom")) {
- EmitCallingConv(CC, O);
+ emitCallingConv(CC, O);
}
}
- EmitArgRegisterLists(O);
+ emitArgRegisterLists(O);
O << "\n#endif // CC_REGISTER_LIST\n";
}
-void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
+void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
const ListInit *CCActions = CC->getValueAsListInit("Actions");
Counter = 0;
@@ -106,8 +106,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
<< std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
// Emit all of the actions, in order.
- for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
- const Record *Action = CCActions->getElementAsRecord(i);
+ for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
+ const Record *Action = CCActions->getElementAsRecord(I);
SwiftAction =
llvm::any_of(Action->getSuperClasses(),
[](const std::pair<const Record *, SMRange> &Class) {
@@ -116,23 +116,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
});
O << "\n";
- EmitAction(Action, indent(2), O);
+ emitAction(Action, indent(2), O);
}
O << "\n return true; // CC didn't match.\n";
O << "}\n";
}
-void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
+void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
raw_ostream &O) {
if (Action->isSubClassOf("CCPredicateAction")) {
O << Indent << "if (";
if (Action->isSubClassOf("CCIfType")) {
const ListInit *VTs = Action->getValueAsListInit("VTs");
- for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
- const Record *VT = VTs->getElementAsRecord(i);
- if (i != 0)
+ for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
+ const Record *VT = VTs->getElementAsRecord(I);
+ if (I != 0)
O << " ||\n " << Indent;
O << "LocVT == " << getEnumName(getValueType(VT));
}
@@ -145,7 +145,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
O << ") {\n";
- EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
+ emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
O << Indent << "}\n";
} else {
if (Action->isSubClassOf("CCDelegateTo")) {
@@ -170,8 +170,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
- std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
+ std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
if (SwiftAction)
AssignedSwiftRegsMap[CurrentAction].insert(Name);
else
@@ -229,16 +229,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i)
- O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(RegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
<< "[] = {\n";
O << Indent << " ";
ListSeparator LSS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
@@ -286,8 +286,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< ShadowRegListNumber << "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
@@ -356,7 +356,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
}
-void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
+void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
// Transitively merge all delegated CCs into AssignedRegsMap.
using EntryTy = std::pair<std::string, std::set<std::string>>;
bool Redo;
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 4d356774f98dcc..74c105986104da 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -52,10 +52,10 @@ class CodeEmitterGen {
public:
CodeEmitterGen(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit);
+ int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit);
std::pair<std::string, std::string>
getInstructionCases(const Record *R, const CodeGenTarget &Target);
void addInstructionCasesForEncoding(const Record *R,
@@ -69,10 +69,10 @@ class CodeEmitterGen {
const CodeGenTarget &Target);
void emitInstructionBaseValues(
- raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
+ raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
void
- emitCaseMap(raw_ostream &o,
+ emitCaseMap(raw_ostream &O,
const std::map<std::string, std::vector<std::string>> &CaseMap);
unsigned BitWidth = 0u;
bool UseAPInt = false;
@@ -81,12 +81,12 @@ class CodeEmitterGen {
// If the VarBitInit at position 'bit' matches the specified variable then
// return the variable bit position. Otherwise return -1.
int CodeEmitterGen::getVariableBit(const std::string &VarName,
- const BitsInit *BI, int bit) {
- if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
+ const BitsInit *BI, int Bit) {
+ if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(Bit))) {
if (const VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
if (VI->getName() == VarName)
return VBI->getBitNum();
- } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
+ } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(Bit))) {
if (VI->getName() == VarName)
return 0;
}
@@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
CodeGenInstruction &CGI = Target.getInstruction(R);
// Determine if VarName actually contributes to the Inst encoding.
- int bit = BI->getNumBits() - 1;
+ int Bit = BI->getNumBits() - 1;
// Scan for a bit that this contributed to.
- for (; bit >= 0;) {
- if (getVariableBit(VarName, BI, bit) != -1)
+ for (; Bit >= 0;) {
+ if (getVariableBit(VarName, BI, Bit) != -1)
break;
- --bit;
+ --Bit;
}
// If we found no bits, ignore this value, otherwise emit the call to get the
// operand encoding.
- if (bit < 0)
+ if (Bit < 0)
return true;
// If the operand matches by name, reference according to that
@@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
// Precalculate the number of lits this variable contributes to in the
// operand. If there is a single lit (consecutive range of bits) we can use a
// destructive sequence on APInt that reduces memory allocations.
- int numOperandLits = 0;
- for (int tmpBit = bit; tmpBit >= 0;) {
- int varBit = getVariableBit(VarName, BI, tmpBit);
+ int NumOperandLits = 0;
+ for (int TmpBit = Bit; TmpBit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, TmpBit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --tmpBit;
+ if (VarBit == -1) {
+ --TmpBit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginVarBit = varBit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--tmpBit; tmpBit >= 0;) {
- varBit = getVariableBit(VarName, BI, tmpBit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--TmpBit; TmpBit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, TmpBit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --tmpBit;
+ --TmpBit;
}
- ++numOperandLits;
+ ++NumOperandLits;
}
unsigned BitOffset = -1;
- for (; bit >= 0;) {
- int varBit = getVariableBit(VarName, BI, bit);
+ for (; Bit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, Bit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --bit;
+ if (VarBit == -1) {
+ --Bit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginInstBit = bit;
- int beginVarBit = varBit;
+ int BeginInstBit = Bit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--bit; bit >= 0;) {
- varBit = getVariableBit(VarName, BI, bit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--Bit; Bit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, Bit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --bit;
+ --Bit;
}
- std::string maskStr;
- int opShift;
+ std::string MaskStr;
+ int OpShift;
- unsigned loBit = beginVarBit - N + 1;
- unsigned hiBit = loBit + N;
- unsigned loInstBit = beginInstBit - N + 1;
- BitOffset = loInstBit;
+ unsigned LoBit = BeginVarBit - N + 1;
+ unsigned HiBit = LoBit + N;
+ unsigned LoInstBit = BeginInstBit - N + 1;
+ BitOffset = LoInstBit;
if (UseAPInt) {
- std::string extractStr;
+ std::string ExtractStr;
if (N >= 64) {
- extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
- itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ");\n";
+ ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " +
+ itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ");\n";
} else {
- extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) +
- ", " + itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n";
+ ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) +
+ ", " + itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n";
}
} else {
- uint64_t opMask = ~(uint64_t)0 >> (64 - N);
- opShift = beginVarBit - N + 1;
- opMask <<= opShift;
- maskStr = "UINT64_C(" + utostr(opMask) + ")";
- opShift = beginInstBit - beginVarBit;
-
- if (numOperandLits == 1) {
- Case += " op &= " + maskStr + ";\n";
- if (opShift > 0) {
- Case += " op <<= " + itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " op >>= " + itostr(-opShift) + ";\n";
+ uint64_t OpMask = ~(uint64_t)0 >> (64 - N);
+ OpShift = BeginVarBit - N + 1;
+ OpMask <<= OpShift;
+ MaskStr = "UINT64_C(" + utostr(OpMask) + ")";
+ OpShift = BeginInstBit - BeginVarBit;
+
+ if (NumOperandLits == 1) {
+ Case += " op &= " + MaskStr + ";\n";
+ if (OpShift > 0) {
+ Case += " op <<= " + itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " op >>= " + itostr(-OpShift) + ";\n";
}
Case += " Value |= op;\n";
} else {
- if (opShift > 0) {
- Case += " Value |= (op & " + maskStr + ") << " +
- itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " Value |= (op & " + maskStr + ") >> " +
- itostr(-opShift) + ";\n";
+ if (OpShift > 0) {
+ Case += " Value |= (op & " + MaskStr + ") << " +
+ itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " Value |= (op & " + MaskStr + ") >> " +
+ itostr(-OpShift) + ";\n";
} else {
- Case += " Value |= (op & " + maskStr + ");\n";
+ Case += " Value |= (op & " + MaskStr + ");\n";
}
}
}
@@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
const CodeGenTarget &Target) {
std::string Case, BitOffsetCase;
- auto append = [&](const std::string &S) {
+ auto Append = [&](const std::string &S) {
Case += S;
BitOffsetCase += S;
};
@@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
// Invoke the interface to obtain the HwMode ID controlling the
// EncodingInfo for the current subtarget. This interface will
// mask off irrelevant HwMode IDs.
- append(" unsigned HwMode = "
+ Append(" unsigned HwMode = "
"STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n");
Case += " switch (HwMode) {\n";
Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); "
@@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R,
Case += " Value = InstBitsByHw[opcode];\n";
}
- append(" switch (HwMode) {\n");
- append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
+ Append(" switch (HwMode) {\n");
+ Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
for (auto &[ModeId, Encoding] : EBM) {
- append(" case " + itostr(ModeId) + ": {\n");
+ Append(" case " + itostr(...
[truncated]
|
|
@llvm/pr-subscribers-backend-risc-v Author: Jerry Sun (jerryyiransun) ChangesPatch is 124.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113318.diff 23 Files Affected:
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 6b8ebf96cdf383..fe8a82e6d7e617 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -25,19 +25,19 @@
using namespace llvm;
/// Collect the full set of implied features for a SubtargetFeature.
-static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
+static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
const Record *Rec) {
assert(Rec->isSubClassOf("SubtargetFeature") &&
"Rec is not a SubtargetFeature");
SeenFeats.insert(Rec);
for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
- CollectImpliedFeatures(SeenFeats, Implied);
+ collectImpliedFeatures(SeenFeats, Implied);
}
-static void CheckFeatureTree(const Record *Root) {
+static void checkFeatureTree(const Record *Root) {
std::set<const Record *> SeenFeats;
- CollectImpliedFeatures(SeenFeats, Root);
+ collectImpliedFeatures(SeenFeats, Root);
// Check that each of the mandatory (implied) features which is an
// ExtensionWithMArch is also enabled by default.
@@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
}
}
-static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
// Look through all SubtargetFeature defs with the given FieldName, and
// collect the set of all Values that that FieldName is set to.
- auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+ auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
llvm::StringSet<> Set;
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
if (Rec->getValueAsString("FieldName") == FieldName) {
@@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
<< "#endif\n\n";
const StringSet<> ARMProcFamilyVals =
- gatherSubtargetFeatureFieldValues("ARMProcFamily");
+ GatherSubtargetFeatureFieldValues("ARMProcFamily");
for (const StringRef &Family : ARMProcFamilyVals.keys())
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
@@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_ARCHITECTURE(ENUM)\n"
<< "#endif\n\n";
// This should correspond to instances of the Architecture tablegen class.
- const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+ const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
for (const StringRef &Arch : ARMArchVals.keys())
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
OS << "\n#undef ARM_ARCHITECTURE\n\n";
@@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- CheckFeatureTree(Arch);
+ checkFeatureTree(Arch);
OS << " {\n"
<< " \"" << Name << "\",\n"
@@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
}
static TableGen::Emitter::Opt
- X("gen-arm-target-def", EmitARMTargetDef,
+ X("gen-arm-target-def", emitArmTargetDef,
"Generate the ARM or AArch64 Architecture information header.");
diff --git a/llvm/utils/TableGen/Attributes.cpp b/llvm/utils/TableGen/Attributes.cpp
index ed00debc398cb9..652dd31a9adb27 100644
--- a/llvm/utils/TableGen/Attributes.cpp
+++ b/llvm/utils/TableGen/Attributes.cpp
@@ -9,7 +9,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
-#include <vector>
using namespace llvm;
#define DEBUG_TYPE "attr-enum"
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index 3718486ff7ad4e..8c347456eb8940 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -17,7 +17,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
-#include <algorithm>
#include <vector>
using namespace llvm;
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index fefc407c354a5d..e44b13f0436313 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -34,12 +34,12 @@ class CallingConvEmitter {
public:
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- void EmitCallingConv(const Record *CC, raw_ostream &O);
- void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
- void EmitArgRegisterLists(raw_ostream &O);
+ void emitCallingConv(const Record *CC, raw_ostream &O);
+ void emitAction(const Record *Action, indent Indent, raw_ostream &O);
+ void emitArgRegisterLists(raw_ostream &O);
};
} // End anonymous namespace
@@ -74,16 +74,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
Records.startTimer("Emit full descriptions");
for (const Record *CC : CCs) {
if (!CC->getValueAsBit("Custom")) {
- EmitCallingConv(CC, O);
+ emitCallingConv(CC, O);
}
}
- EmitArgRegisterLists(O);
+ emitArgRegisterLists(O);
O << "\n#endif // CC_REGISTER_LIST\n";
}
-void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
+void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
const ListInit *CCActions = CC->getValueAsListInit("Actions");
Counter = 0;
@@ -106,8 +106,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
<< std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
// Emit all of the actions, in order.
- for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
- const Record *Action = CCActions->getElementAsRecord(i);
+ for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
+ const Record *Action = CCActions->getElementAsRecord(I);
SwiftAction =
llvm::any_of(Action->getSuperClasses(),
[](const std::pair<const Record *, SMRange> &Class) {
@@ -116,23 +116,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
});
O << "\n";
- EmitAction(Action, indent(2), O);
+ emitAction(Action, indent(2), O);
}
O << "\n return true; // CC didn't match.\n";
O << "}\n";
}
-void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
+void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
raw_ostream &O) {
if (Action->isSubClassOf("CCPredicateAction")) {
O << Indent << "if (";
if (Action->isSubClassOf("CCIfType")) {
const ListInit *VTs = Action->getValueAsListInit("VTs");
- for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
- const Record *VT = VTs->getElementAsRecord(i);
- if (i != 0)
+ for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
+ const Record *VT = VTs->getElementAsRecord(I);
+ if (I != 0)
O << " ||\n " << Indent;
O << "LocVT == " << getEnumName(getValueType(VT));
}
@@ -145,7 +145,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
O << ") {\n";
- EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
+ emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
O << Indent << "}\n";
} else {
if (Action->isSubClassOf("CCDelegateTo")) {
@@ -170,8 +170,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
- std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
+ std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
if (SwiftAction)
AssignedSwiftRegsMap[CurrentAction].insert(Name);
else
@@ -229,16 +229,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i)
- O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(RegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
<< "[] = {\n";
O << Indent << " ";
ListSeparator LSS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
@@ -286,8 +286,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< ShadowRegListNumber << "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
@@ -356,7 +356,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
}
-void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
+void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
// Transitively merge all delegated CCs into AssignedRegsMap.
using EntryTy = std::pair<std::string, std::set<std::string>>;
bool Redo;
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 4d356774f98dcc..74c105986104da 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -52,10 +52,10 @@ class CodeEmitterGen {
public:
CodeEmitterGen(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit);
+ int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit);
std::pair<std::string, std::string>
getInstructionCases(const Record *R, const CodeGenTarget &Target);
void addInstructionCasesForEncoding(const Record *R,
@@ -69,10 +69,10 @@ class CodeEmitterGen {
const CodeGenTarget &Target);
void emitInstructionBaseValues(
- raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
+ raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
void
- emitCaseMap(raw_ostream &o,
+ emitCaseMap(raw_ostream &O,
const std::map<std::string, std::vector<std::string>> &CaseMap);
unsigned BitWidth = 0u;
bool UseAPInt = false;
@@ -81,12 +81,12 @@ class CodeEmitterGen {
// If the VarBitInit at position 'bit' matches the specified variable then
// return the variable bit position. Otherwise return -1.
int CodeEmitterGen::getVariableBit(const std::string &VarName,
- const BitsInit *BI, int bit) {
- if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
+ const BitsInit *BI, int Bit) {
+ if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(Bit))) {
if (const VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
if (VI->getName() == VarName)
return VBI->getBitNum();
- } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
+ } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(Bit))) {
if (VI->getName() == VarName)
return 0;
}
@@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
CodeGenInstruction &CGI = Target.getInstruction(R);
// Determine if VarName actually contributes to the Inst encoding.
- int bit = BI->getNumBits() - 1;
+ int Bit = BI->getNumBits() - 1;
// Scan for a bit that this contributed to.
- for (; bit >= 0;) {
- if (getVariableBit(VarName, BI, bit) != -1)
+ for (; Bit >= 0;) {
+ if (getVariableBit(VarName, BI, Bit) != -1)
break;
- --bit;
+ --Bit;
}
// If we found no bits, ignore this value, otherwise emit the call to get the
// operand encoding.
- if (bit < 0)
+ if (Bit < 0)
return true;
// If the operand matches by name, reference according to that
@@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
// Precalculate the number of lits this variable contributes to in the
// operand. If there is a single lit (consecutive range of bits) we can use a
// destructive sequence on APInt that reduces memory allocations.
- int numOperandLits = 0;
- for (int tmpBit = bit; tmpBit >= 0;) {
- int varBit = getVariableBit(VarName, BI, tmpBit);
+ int NumOperandLits = 0;
+ for (int TmpBit = Bit; TmpBit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, TmpBit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --tmpBit;
+ if (VarBit == -1) {
+ --TmpBit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginVarBit = varBit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--tmpBit; tmpBit >= 0;) {
- varBit = getVariableBit(VarName, BI, tmpBit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--TmpBit; TmpBit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, TmpBit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --tmpBit;
+ --TmpBit;
}
- ++numOperandLits;
+ ++NumOperandLits;
}
unsigned BitOffset = -1;
- for (; bit >= 0;) {
- int varBit = getVariableBit(VarName, BI, bit);
+ for (; Bit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, Bit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --bit;
+ if (VarBit == -1) {
+ --Bit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginInstBit = bit;
- int beginVarBit = varBit;
+ int BeginInstBit = Bit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--bit; bit >= 0;) {
- varBit = getVariableBit(VarName, BI, bit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--Bit; Bit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, Bit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --bit;
+ --Bit;
}
- std::string maskStr;
- int opShift;
+ std::string MaskStr;
+ int OpShift;
- unsigned loBit = beginVarBit - N + 1;
- unsigned hiBit = loBit + N;
- unsigned loInstBit = beginInstBit - N + 1;
- BitOffset = loInstBit;
+ unsigned LoBit = BeginVarBit - N + 1;
+ unsigned HiBit = LoBit + N;
+ unsigned LoInstBit = BeginInstBit - N + 1;
+ BitOffset = LoInstBit;
if (UseAPInt) {
- std::string extractStr;
+ std::string ExtractStr;
if (N >= 64) {
- extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
- itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ");\n";
+ ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " +
+ itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ");\n";
} else {
- extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) +
- ", " + itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n";
+ ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) +
+ ", " + itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n";
}
} else {
- uint64_t opMask = ~(uint64_t)0 >> (64 - N);
- opShift = beginVarBit - N + 1;
- opMask <<= opShift;
- maskStr = "UINT64_C(" + utostr(opMask) + ")";
- opShift = beginInstBit - beginVarBit;
-
- if (numOperandLits == 1) {
- Case += " op &= " + maskStr + ";\n";
- if (opShift > 0) {
- Case += " op <<= " + itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " op >>= " + itostr(-opShift) + ";\n";
+ uint64_t OpMask = ~(uint64_t)0 >> (64 - N);
+ OpShift = BeginVarBit - N + 1;
+ OpMask <<= OpShift;
+ MaskStr = "UINT64_C(" + utostr(OpMask) + ")";
+ OpShift = BeginInstBit - BeginVarBit;
+
+ if (NumOperandLits == 1) {
+ Case += " op &= " + MaskStr + ";\n";
+ if (OpShift > 0) {
+ Case += " op <<= " + itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " op >>= " + itostr(-OpShift) + ";\n";
}
Case += " Value |= op;\n";
} else {
- if (opShift > 0) {
- Case += " Value |= (op & " + maskStr + ") << " +
- itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " Value |= (op & " + maskStr + ") >> " +
- itostr(-opShift) + ";\n";
+ if (OpShift > 0) {
+ Case += " Value |= (op & " + MaskStr + ") << " +
+ itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " Value |= (op & " + MaskStr + ") >> " +
+ itostr(-OpShift) + ";\n";
} else {
- Case += " Value |= (op & " + maskStr + ");\n";
+ Case += " Value |= (op & " + MaskStr + ");\n";
}
}
}
@@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
const CodeGenTarget &Target) {
std::string Case, BitOffsetCase;
- auto append = [&](const std::string &S) {
+ auto Append = [&](const std::string &S) {
Case += S;
BitOffsetCase += S;
};
@@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
// Invoke the interface to obtain the HwMode ID controlling the
// EncodingInfo for the current subtarget. This interface will
// mask off irrelevant HwMode IDs.
- append(" unsigned HwMode = "
+ Append(" unsigned HwMode = "
"STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n");
Case += " switch (HwMode) {\n";
Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); "
@@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R,
Case += " Value = InstBitsByHw[opcode];\n";
}
- append(" switch (HwMode) {\n");
- append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
+ Append(" switch (HwMode) {\n");
+ Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
for (auto &[ModeId, Encoding] : EBM) {
- append(" case " + itostr(ModeId) + ": {\n");
+ Append(" case " + itostr(...
[truncated]
|
|
@llvm/pr-subscribers-backend-directx Author: Jerry Sun (jerryyiransun) ChangesPatch is 124.11 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/113318.diff 23 Files Affected:
diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
index 6b8ebf96cdf383..fe8a82e6d7e617 100644
--- a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp
@@ -25,19 +25,19 @@
using namespace llvm;
/// Collect the full set of implied features for a SubtargetFeature.
-static void CollectImpliedFeatures(std::set<const Record *> &SeenFeats,
+static void collectImpliedFeatures(std::set<const Record *> &SeenFeats,
const Record *Rec) {
assert(Rec->isSubClassOf("SubtargetFeature") &&
"Rec is not a SubtargetFeature");
SeenFeats.insert(Rec);
for (const Record *Implied : Rec->getValueAsListOfDefs("Implies"))
- CollectImpliedFeatures(SeenFeats, Implied);
+ collectImpliedFeatures(SeenFeats, Implied);
}
-static void CheckFeatureTree(const Record *Root) {
+static void checkFeatureTree(const Record *Root) {
std::set<const Record *> SeenFeats;
- CollectImpliedFeatures(SeenFeats, Root);
+ collectImpliedFeatures(SeenFeats, Root);
// Check that each of the mandatory (implied) features which is an
// ExtensionWithMArch is also enabled by default.
@@ -53,12 +53,12 @@ static void CheckFeatureTree(const Record *Root) {
}
}
-static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
+static void emitArmTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n";
// Look through all SubtargetFeature defs with the given FieldName, and
// collect the set of all Values that that FieldName is set to.
- auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
+ auto GatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) {
llvm::StringSet<> Set;
for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) {
if (Rec->getValueAsString("FieldName") == FieldName) {
@@ -88,7 +88,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_PROCESSOR_FAMILY(ENUM)\n"
<< "#endif\n\n";
const StringSet<> ARMProcFamilyVals =
- gatherSubtargetFeatureFieldValues("ARMProcFamily");
+ GatherSubtargetFeatureFieldValues("ARMProcFamily");
for (const StringRef &Family : ARMProcFamilyVals.keys())
OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n";
OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n";
@@ -97,7 +97,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
<< "#define ARM_ARCHITECTURE(ENUM)\n"
<< "#endif\n\n";
// This should correspond to instances of the Architecture tablegen class.
- const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch");
+ const StringSet<> ARMArchVals = GatherSubtargetFeatureFieldValues("ARMArch");
for (const StringRef &Arch : ARMArchVals.keys())
OS << "ARM_ARCHITECTURE(" << Arch << ")\n";
OS << "\n#undef ARM_ARCHITECTURE\n\n";
@@ -315,7 +315,7 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
- CheckFeatureTree(Arch);
+ checkFeatureTree(Arch);
OS << " {\n"
<< " \"" << Name << "\",\n"
@@ -343,5 +343,5 @@ static void EmitARMTargetDef(const RecordKeeper &RK, raw_ostream &OS) {
}
static TableGen::Emitter::Opt
- X("gen-arm-target-def", EmitARMTargetDef,
+ X("gen-arm-target-def", emitArmTargetDef,
"Generate the ARM or AArch64 Architecture information header.");
diff --git a/llvm/utils/TableGen/Attributes.cpp b/llvm/utils/TableGen/Attributes.cpp
index ed00debc398cb9..652dd31a9adb27 100644
--- a/llvm/utils/TableGen/Attributes.cpp
+++ b/llvm/utils/TableGen/Attributes.cpp
@@ -9,7 +9,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
-#include <vector>
using namespace llvm;
#define DEBUG_TYPE "attr-enum"
diff --git a/llvm/utils/TableGen/CTagsEmitter.cpp b/llvm/utils/TableGen/CTagsEmitter.cpp
index 3718486ff7ad4e..8c347456eb8940 100644
--- a/llvm/utils/TableGen/CTagsEmitter.cpp
+++ b/llvm/utils/TableGen/CTagsEmitter.cpp
@@ -17,7 +17,6 @@
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
-#include <algorithm>
#include <vector>
using namespace llvm;
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index fefc407c354a5d..e44b13f0436313 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -34,12 +34,12 @@ class CallingConvEmitter {
public:
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- void EmitCallingConv(const Record *CC, raw_ostream &O);
- void EmitAction(const Record *Action, indent Indent, raw_ostream &O);
- void EmitArgRegisterLists(raw_ostream &O);
+ void emitCallingConv(const Record *CC, raw_ostream &O);
+ void emitAction(const Record *Action, indent Indent, raw_ostream &O);
+ void emitArgRegisterLists(raw_ostream &O);
};
} // End anonymous namespace
@@ -74,16 +74,16 @@ void CallingConvEmitter::run(raw_ostream &O) {
Records.startTimer("Emit full descriptions");
for (const Record *CC : CCs) {
if (!CC->getValueAsBit("Custom")) {
- EmitCallingConv(CC, O);
+ emitCallingConv(CC, O);
}
}
- EmitArgRegisterLists(O);
+ emitArgRegisterLists(O);
O << "\n#endif // CC_REGISTER_LIST\n";
}
-void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
+void CallingConvEmitter::emitCallingConv(const Record *CC, raw_ostream &O) {
const ListInit *CCActions = CC->getValueAsListInit("Actions");
Counter = 0;
@@ -106,8 +106,8 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
<< std::string(Pad, ' ') << "MVT LocVT, CCValAssign::LocInfo LocInfo,\n"
<< std::string(Pad, ' ') << "ISD::ArgFlagsTy ArgFlags, CCState &State) {\n";
// Emit all of the actions, in order.
- for (unsigned i = 0, e = CCActions->size(); i != e; ++i) {
- const Record *Action = CCActions->getElementAsRecord(i);
+ for (unsigned I = 0, E = CCActions->size(); I != E; ++I) {
+ const Record *Action = CCActions->getElementAsRecord(I);
SwiftAction =
llvm::any_of(Action->getSuperClasses(),
[](const std::pair<const Record *, SMRange> &Class) {
@@ -116,23 +116,23 @@ void CallingConvEmitter::EmitCallingConv(const Record *CC, raw_ostream &O) {
});
O << "\n";
- EmitAction(Action, indent(2), O);
+ emitAction(Action, indent(2), O);
}
O << "\n return true; // CC didn't match.\n";
O << "}\n";
}
-void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
+void CallingConvEmitter::emitAction(const Record *Action, indent Indent,
raw_ostream &O) {
if (Action->isSubClassOf("CCPredicateAction")) {
O << Indent << "if (";
if (Action->isSubClassOf("CCIfType")) {
const ListInit *VTs = Action->getValueAsListInit("VTs");
- for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
- const Record *VT = VTs->getElementAsRecord(i);
- if (i != 0)
+ for (unsigned I = 0, E = VTs->size(); I != E; ++I) {
+ const Record *VT = VTs->getElementAsRecord(I);
+ if (I != 0)
O << " ||\n " << Indent;
O << "LocVT == " << getEnumName(getValueType(VT));
}
@@ -145,7 +145,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
O << ") {\n";
- EmitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
+ emitAction(Action->getValueAsDef("SubAction"), Indent + 2, O);
O << Indent << "}\n";
} else {
if (Action->isSubClassOf("CCDelegateTo")) {
@@ -170,8 +170,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i) {
- std::string Name = getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I) {
+ std::string Name = getQualifiedName(RegList->getElementAsRecord(I));
if (SwiftAction)
AssignedSwiftRegsMap[CurrentAction].insert(Name);
else
@@ -229,16 +229,16 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = RegList->size(); i != e; ++i)
- O << LS << getQualifiedName(RegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = RegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(RegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "static const MCPhysReg RegList" << ShadowRegListNumber
<< "[] = {\n";
O << Indent << " ";
ListSeparator LSS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LSS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "if (MCRegister Reg = State.AllocateReg(RegList"
@@ -286,8 +286,8 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
<< ShadowRegListNumber << "[] = {\n";
O << Indent << " ";
ListSeparator LS;
- for (unsigned i = 0, e = ShadowRegList->size(); i != e; ++i)
- O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(i));
+ for (unsigned I = 0, E = ShadowRegList->size(); I != E; ++I)
+ O << LS << getQualifiedName(ShadowRegList->getElementAsRecord(I));
O << "\n" << Indent << "};\n";
O << Indent << "int64_t Offset" << ++Counter << " = State.AllocateStack("
@@ -356,7 +356,7 @@ void CallingConvEmitter::EmitAction(const Record *Action, indent Indent,
}
}
-void CallingConvEmitter::EmitArgRegisterLists(raw_ostream &O) {
+void CallingConvEmitter::emitArgRegisterLists(raw_ostream &O) {
// Transitively merge all delegated CCs into AssignedRegsMap.
using EntryTy = std::pair<std::string, std::set<std::string>>;
bool Redo;
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 4d356774f98dcc..74c105986104da 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -52,10 +52,10 @@ class CodeEmitterGen {
public:
CodeEmitterGen(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
private:
- int getVariableBit(const std::string &VarName, const BitsInit *BI, int bit);
+ int getVariableBit(const std::string &VarName, const BitsInit *BI, int Bit);
std::pair<std::string, std::string>
getInstructionCases(const Record *R, const CodeGenTarget &Target);
void addInstructionCasesForEncoding(const Record *R,
@@ -69,10 +69,10 @@ class CodeEmitterGen {
const CodeGenTarget &Target);
void emitInstructionBaseValues(
- raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
+ raw_ostream &O, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
const CodeGenTarget &Target, unsigned HwMode = DefaultMode);
void
- emitCaseMap(raw_ostream &o,
+ emitCaseMap(raw_ostream &O,
const std::map<std::string, std::vector<std::string>> &CaseMap);
unsigned BitWidth = 0u;
bool UseAPInt = false;
@@ -81,12 +81,12 @@ class CodeEmitterGen {
// If the VarBitInit at position 'bit' matches the specified variable then
// return the variable bit position. Otherwise return -1.
int CodeEmitterGen::getVariableBit(const std::string &VarName,
- const BitsInit *BI, int bit) {
- if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
+ const BitsInit *BI, int Bit) {
+ if (const VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(Bit))) {
if (const VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
if (VI->getName() == VarName)
return VBI->getBitNum();
- } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
+ } else if (const VarInit *VI = dyn_cast<VarInit>(BI->getBit(Bit))) {
if (VI->getName() == VarName)
return 0;
}
@@ -104,19 +104,19 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
CodeGenInstruction &CGI = Target.getInstruction(R);
// Determine if VarName actually contributes to the Inst encoding.
- int bit = BI->getNumBits() - 1;
+ int Bit = BI->getNumBits() - 1;
// Scan for a bit that this contributed to.
- for (; bit >= 0;) {
- if (getVariableBit(VarName, BI, bit) != -1)
+ for (; Bit >= 0;) {
+ if (getVariableBit(VarName, BI, Bit) != -1)
break;
- --bit;
+ --Bit;
}
// If we found no bits, ignore this value, otherwise emit the call to get the
// operand encoding.
- if (bit < 0)
+ if (Bit < 0)
return true;
// If the operand matches by name, reference according to that
@@ -175,97 +175,97 @@ bool CodeEmitterGen::addCodeToMergeInOperand(const Record *R,
// Precalculate the number of lits this variable contributes to in the
// operand. If there is a single lit (consecutive range of bits) we can use a
// destructive sequence on APInt that reduces memory allocations.
- int numOperandLits = 0;
- for (int tmpBit = bit; tmpBit >= 0;) {
- int varBit = getVariableBit(VarName, BI, tmpBit);
+ int NumOperandLits = 0;
+ for (int TmpBit = Bit; TmpBit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, TmpBit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --tmpBit;
+ if (VarBit == -1) {
+ --TmpBit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginVarBit = varBit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--tmpBit; tmpBit >= 0;) {
- varBit = getVariableBit(VarName, BI, tmpBit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--TmpBit; TmpBit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, TmpBit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --tmpBit;
+ --TmpBit;
}
- ++numOperandLits;
+ ++NumOperandLits;
}
unsigned BitOffset = -1;
- for (; bit >= 0;) {
- int varBit = getVariableBit(VarName, BI, bit);
+ for (; Bit >= 0;) {
+ int VarBit = getVariableBit(VarName, BI, Bit);
// If this bit isn't from a variable, skip it.
- if (varBit == -1) {
- --bit;
+ if (VarBit == -1) {
+ --Bit;
continue;
}
// Figure out the consecutive range of bits covered by this operand, in
// order to generate better encoding code.
- int beginInstBit = bit;
- int beginVarBit = varBit;
+ int BeginInstBit = Bit;
+ int BeginVarBit = VarBit;
int N = 1;
- for (--bit; bit >= 0;) {
- varBit = getVariableBit(VarName, BI, bit);
- if (varBit == -1 || varBit != (beginVarBit - N))
+ for (--Bit; Bit >= 0;) {
+ VarBit = getVariableBit(VarName, BI, Bit);
+ if (VarBit == -1 || VarBit != (BeginVarBit - N))
break;
++N;
- --bit;
+ --Bit;
}
- std::string maskStr;
- int opShift;
+ std::string MaskStr;
+ int OpShift;
- unsigned loBit = beginVarBit - N + 1;
- unsigned hiBit = loBit + N;
- unsigned loInstBit = beginInstBit - N + 1;
- BitOffset = loInstBit;
+ unsigned LoBit = BeginVarBit - N + 1;
+ unsigned HiBit = LoBit + N;
+ unsigned LoInstBit = BeginInstBit - N + 1;
+ BitOffset = LoInstBit;
if (UseAPInt) {
- std::string extractStr;
+ std::string ExtractStr;
if (N >= 64) {
- extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
- itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ");\n";
+ ExtractStr = "op.extractBits(" + itostr(HiBit - LoBit) + ", " +
+ itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ");\n";
} else {
- extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) +
- ", " + itostr(loBit) + ")";
- Case += " Value.insertBits(" + extractStr + ", " +
- itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n";
+ ExtractStr = "op.extractBitsAsZExtValue(" + itostr(HiBit - LoBit) +
+ ", " + itostr(LoBit) + ")";
+ Case += " Value.insertBits(" + ExtractStr + ", " +
+ itostr(LoInstBit) + ", " + itostr(HiBit - LoBit) + ");\n";
}
} else {
- uint64_t opMask = ~(uint64_t)0 >> (64 - N);
- opShift = beginVarBit - N + 1;
- opMask <<= opShift;
- maskStr = "UINT64_C(" + utostr(opMask) + ")";
- opShift = beginInstBit - beginVarBit;
-
- if (numOperandLits == 1) {
- Case += " op &= " + maskStr + ";\n";
- if (opShift > 0) {
- Case += " op <<= " + itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " op >>= " + itostr(-opShift) + ";\n";
+ uint64_t OpMask = ~(uint64_t)0 >> (64 - N);
+ OpShift = BeginVarBit - N + 1;
+ OpMask <<= OpShift;
+ MaskStr = "UINT64_C(" + utostr(OpMask) + ")";
+ OpShift = BeginInstBit - BeginVarBit;
+
+ if (NumOperandLits == 1) {
+ Case += " op &= " + MaskStr + ";\n";
+ if (OpShift > 0) {
+ Case += " op <<= " + itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " op >>= " + itostr(-OpShift) + ";\n";
}
Case += " Value |= op;\n";
} else {
- if (opShift > 0) {
- Case += " Value |= (op & " + maskStr + ") << " +
- itostr(opShift) + ";\n";
- } else if (opShift < 0) {
- Case += " Value |= (op & " + maskStr + ") >> " +
- itostr(-opShift) + ";\n";
+ if (OpShift > 0) {
+ Case += " Value |= (op & " + MaskStr + ") << " +
+ itostr(OpShift) + ";\n";
+ } else if (OpShift < 0) {
+ Case += " Value |= (op & " + MaskStr + ") >> " +
+ itostr(-OpShift) + ";\n";
} else {
- Case += " Value |= (op & " + maskStr + ");\n";
+ Case += " Value |= (op & " + MaskStr + ");\n";
}
}
}
@@ -285,7 +285,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
const CodeGenTarget &Target) {
std::string Case, BitOffsetCase;
- auto append = [&](const std::string &S) {
+ auto Append = [&](const std::string &S) {
Case += S;
BitOffsetCase += S;
};
@@ -298,7 +298,7 @@ CodeEmitterGen::getInstructionCases(const Record *R,
// Invoke the interface to obtain the HwMode ID controlling the
// EncodingInfo for the current subtarget. This interface will
// mask off irrelevant HwMode IDs.
- append(" unsigned HwMode = "
+ Append(" unsigned HwMode = "
"STI.getHwMode(MCSubtargetInfo::HwMode_EncodingInfo);\n");
Case += " switch (HwMode) {\n";
Case += " default: llvm_unreachable(\"Unknown hardware mode!\"); "
@@ -328,16 +328,16 @@ CodeEmitterGen::getInstructionCases(const Record *R,
Case += " Value = InstBitsByHw[opcode];\n";
}
- append(" switch (HwMode) {\n");
- append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
+ Append(" switch (HwMode) {\n");
+ Append(" default: llvm_unreachable(\"Unhandled HwMode\");\n");
for (auto &[ModeId, Encoding] : EBM) {
- append(" case " + itostr(ModeId) + ": {\n");
+ Append(" case " + itostr(...
[truncated]
|
jerryyiransun
changed the title
clang-tidy checks and remove unused importsclang-tidy checks and remove unused imports
jerryyiransun
changed the title
clang-tidy checks and remove unused importsclang-tidy checks and remove unused imports
jurahul
reviewed
Oct 22, 2024
| @@ -34,12 +34,12 @@ class CallingConvEmitter { | |||
| public: | |||
| explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {} | |||
|
|
|||
| void run(raw_ostream &o); | |||
| void run(raw_ostream &O); | |||
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nit: can this be OS. I've seen that as commonly used variable name for raw_ostream?
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Do you want me to change all &O to &OS in the file? There are quite a few methods in this file that have raw_ostream as parameter and they are all defined to be &O
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Yes, since you are changing the, you might as well use the preferred name
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@jurahul should I create a new PR for this change? It looks like there are few other files that also needs this modification. I think it might introduce too many changed files in this PR.
|
The changes themselves are fine. Such large-scale commits are usually avoided, but we've gone through various renaming efforts in the past. I'm fine with committing this, but let's check with @Paul-C-Anagnostopoulos. |
|
What’s the best way to do this? Split it per file?
…On Tue, Oct 22, 2024 at 7:47 AM Krzysztof Parzyszek < ***@***.***> wrote:
The changes themselves are fine. Such large-scale commits are usually
avoided, but we've gone through various renaming efforts in the past. I'm
fine with committing this, but let's check with @Paul-C-Anagnostopoulos
<https://github.com/Paul-C-Anagnostopoulos>.
—
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The removal of unused includes could be separated into a new PR. That would reduce the number of touched files, without creating a flood of PRs. |
The issue is that "formatting" commits introduce noise in the file history, which can affect things like The "preferred" approach it to tack it on top of some functional commit, i.e. make such changes to the code that the commit was changing anyway. The downside is that this process may never finish all the intended changes. Paul is the code owner of TableGen, so I defer to him to make the final decision. This change is fine if there is a consensus to do it, and I'm not opposed. Edit: Paul may be MIA (his profile shows 0 commits in the past year). If he doesn't reply in a few days, this PR can be brought up on discourse. |
|
IMO, discouraging such changes to preserve git history is not a great
argument. We have tools like git blame which help recover the history. Yes
you may have to make a few more hops in the git blame chain. Also packaging
NFC and functional changes together is also not recommended AFAICT.
…On Tue, Oct 22, 2024 at 8:13 AM Krzysztof Parzyszek < ***@***.***> wrote:
What’s the best way to do this? Split it per file?
The issue is that "formatting" commits introduce noise in the file
history, which can affect things like git blame. There are ways around
it, for example, blame allows you to give a list of commits to ignore (we
have it in .git-blame-ignore-revs), but you still have to manually
provide that option. Some tools may not be doing it, and so they can trace
some change back to an NFC commit.
The "preferred" approach it to tack it on top of some functional commit,
i.e. make such changes to the code that the commit was changing anyway. The
downside is that this process may never finish all the intended changes.
Paul is the code owner of TableGen, so I defer to him to make the final
decision. This change is fine if there is a consensus to do it, and I'm not
opposed.
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|
I'm not actively working on TableGen these days, so you don't really need my opinion. But these cleanups are a great idea and so go for it. |
|
Thanks. Though it might to get clarity on LLVM’s policy for such changes if
any. I’ll check if this has come up before and if there is any existing
guidance.
…On Tue, Oct 22, 2024 at 8:28 AM Paul C. Anagnostopoulos < ***@***.***> wrote:
I'm not actively working on TableGen these days, so you don't really need
my opinion. But these cleanups are a great idea and so go for it.
—
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|
https://discourse.llvm.org/t/widescale-clang-tidy-or-similar-based-cleanup/44527
Looks like wide scale code reformatting is discouraged but other cleanups
like this one are welcome.
For this case, if we can split into 2: unused header removal and rename
things to conform to LLVM coding standards seems reasonable.
…On Tue, Oct 22, 2024 at 8:43 AM Rahul Joshi ***@***.***> wrote:
Thanks. Though it might to get clarity on LLVM’s policy for such changes
if any. I’ll check if this has come up before and if there is any existing
guidance.
On Tue, Oct 22, 2024 at 8:28 AM Paul C. Anagnostopoulos <
***@***.***> wrote:
> I'm not actively working on TableGen these days, so you don't really need
> my opinion. But these cleanups are a great idea and so go for it.
>
> —
> Reply to this email directly, view it on GitHub
> <#113318 (comment)>,
> or unsubscribe
> <https://github.com/notifications/unsubscribe-auth/APRMUB3SSILWRLHT64LLPL3Z4ZVKRAVCNFSM6AAAAABQMSTYAKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDIMRZGU4TQMRZGU>
> .
> You are receiving this because your review was requested.Message ID:
> ***@***.***>
>
|
|
For the git blame issue, I wonder if git-blame can be taught to skip
commits with NFC keyword in the short description. On that topic, instead
of [code-cleanup] can you use [NFC]?
…On Tue, Oct 22, 2024 at 9:00 AM Rahul Joshi ***@***.***> wrote:
https://discourse.llvm.org/t/widescale-clang-tidy-or-similar-based-cleanup/44527
Looks like wide scale code reformatting is discouraged but other cleanups
like this one are welcome.
For this case, if we can split into 2: unused header removal and rename
things to conform to LLVM coding standards seems reasonable.
On Tue, Oct 22, 2024 at 8:43 AM Rahul Joshi ***@***.***> wrote:
> Thanks. Though it might to get clarity on LLVM’s policy for such changes
> if any. I’ll check if this has come up before and if there is any existing
> guidance.
>
> On Tue, Oct 22, 2024 at 8:28 AM Paul C. Anagnostopoulos <
> ***@***.***> wrote:
>
>> I'm not actively working on TableGen these days, so you don't really
>> need my opinion. But these cleanups are a great idea and so go for it.
>>
>> —
>> Reply to this email directly, view it on GitHub
>> <#113318 (comment)>,
>> or unsubscribe
>> <https://github.com/notifications/unsubscribe-auth/APRMUB3SSILWRLHT64LLPL3Z4ZVKRAVCNFSM6AAAAABQMSTYAKVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDIMRZGU4TQMRZGU>
>> .
>> You are receiving this because your review was requested.Message ID:
>> ***@***.***>
>>
>
|
|
NFC doesn't mean ignorable. They can have a large amount of churn that's significant for blame, and they can end up not being NFC. |
|
Please also see https://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly (@tmatheson-arm made a comment about this but I don't see it). Some of the changes are violating the LLVM's convention for names |
jerryyiransun
changed the title
clang-tidy checks and remove unused importsclang-tidy checks and remove unused imports
|
Thanks for the feedback, I will review the webpage and make changes accordingly.
|
It was probably deleted by the author. |
Yes sorry, I did comment but then upon double checking it looked like I was wrong, so I deleted the comment to try and avoid confusion. |
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|
I've extracted the commit for removing unused imports to #113725 as requested. |
jerryyiransun
changed the title
clang-tidy checks and remove unused importsclang-tidy checks
|
Sounds good. Breaking it into smaller PR for independent changes is welcome.
…On Fri, Oct 25, 2024 at 12:07 PM Jerry Sun ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In llvm/utils/TableGen/CallingConvEmitter.cpp
<#113318 (comment)>:
> @@ -34,12 +34,12 @@ class CallingConvEmitter {
public:
explicit CallingConvEmitter(const RecordKeeper &R) : Records(R) {}
- void run(raw_ostream &o);
+ void run(raw_ostream &O);
@jurahul <https://github.com/jurahul> should I create a new PR for this
change? It looks like there are few other files that also needs this
modification. I think it might introduce too many changed files in this PR.
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LGTM to me, but let's wait for other folks to chime in. |
arsenm
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split PR as requested from #113318. Removes unused imports in TableGen BE
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split PR as requested from llvm#113318. Removes unused imports in TableGen BE
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…cks (llvm#113318) Code cleanups for TableGen files, changes includes function names, variable names and unused imports. --------- Co-authored-by: Matt Arsenault <[email protected]>
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Code cleanups for TableGen files, changes includes function names, variable names and unused imports.