AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups #113751

arsenm · 2024-10-26T04:13:51Z

0 does not make sense as a value for this to be, much less the default.
Also stop emitting each individual field if it is the default, rather than
if any element was the default. Also fix the name of the test since it didn't
exactly match the real attribute name.

arsenm · 2024-10-26T04:14:11Z

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llvmbot · 2024-10-26T04:14:53Z

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

0 does not make sense as a value for this to be, much less the default.
Also stop emitting each individual field if it is the default, rather than
if any element was the default. Also fix the name of the test since it didn't
exactly match the real attribute name.

Full diff: https://github.com/llvm/llvm-project/pull/113751.diff

5 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp (+10-5)
(modified) llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp (+2-1)
(modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+4-3)
(modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+2-1)
(renamed) llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll (+58)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
index bd418efcb83cb2..440d6f9a503279 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
@@ -504,14 +504,19 @@ MetadataStreamerMsgPackV4::getHSAKernelProps(const MachineFunction &MF,
 
   Kern[".max_flat_workgroup_size"] =
       Kern.getDocument()->getNode(MFI.getMaxFlatWorkGroupSize());
-  unsigned NumWGX = MFI.getMaxNumWorkGroupsX();
-  unsigned NumWGY = MFI.getMaxNumWorkGroupsY();
-  unsigned NumWGZ = MFI.getMaxNumWorkGroupsZ();
-  if (NumWGX != 0 && NumWGY != 0 && NumWGZ != 0) {
+
+  uint32_t NumWGX = MFI.getMaxNumWorkGroupsX();
+  uint32_t NumWGY = MFI.getMaxNumWorkGroupsY();
+  uint32_t NumWGZ = MFI.getMaxNumWorkGroupsZ();
+  if (NumWGX != std::numeric_limits<uint32_t>::max())
     Kern[".max_num_workgroups_x"] = Kern.getDocument()->getNode(NumWGX);
+
+  if (NumWGY != std::numeric_limits<uint32_t>::max())
     Kern[".max_num_workgroups_y"] = Kern.getDocument()->getNode(NumWGY);
+
+  if (NumWGZ != std::numeric_limits<uint32_t>::max())
     Kern[".max_num_workgroups_z"] = Kern.getDocument()->getNode(NumWGZ);
-  }
+
   Kern[".sgpr_spill_count"] =
       Kern.getDocument()->getNode(MFI.getNumSpilledSGPRs());
   Kern[".vgpr_spill_count"] =
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 961a9220b48d6b..54b17ca2cffb15 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -371,5 +371,6 @@ const AMDGPUSubtarget &AMDGPUSubtarget::get(const TargetMachine &TM, const Funct
 
 SmallVector<unsigned>
 AMDGPUSubtarget::getMaxNumWorkGroups(const Function &F) const {
-  return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3);
+  return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3,
+                                        std::numeric_limits<uint32_t>::max());
 }
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 20a81a3135f0b2..c167e27ab07a51 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1307,15 +1307,16 @@ getIntegerPairAttribute(const Function &F, StringRef Name,
 }
 
 SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
-                                             unsigned Size) {
+                                             unsigned Size,
+                                             unsigned DefaultVal) {
   assert(Size > 2);
-  SmallVector<unsigned> Default(Size, 0);
+  SmallVector<unsigned> Default(Size, DefaultVal);
 
   Attribute A = F.getFnAttribute(Name);
   if (!A.isStringAttribute())
     return Default;
 
-  SmallVector<unsigned> Vals(Size, 0);
+  SmallVector<unsigned> Vals(Size, DefaultVal);
 
   LLVMContext &Ctx = F.getContext();
 
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index d1d84394cc0705..beebe320b2cf3a 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -919,7 +919,8 @@ getIntegerPairAttribute(const Function &F, StringRef Name,
 ///
 /// \returns false if any error occurs.
 SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
-                                             unsigned Size);
+                                             unsigned Size,
+                                             unsigned DefaultVal = 0);
 
 /// Represents the counter values to wait for in an s_waitcnt instruction.
 ///
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
similarity index 58%
rename from llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
rename to llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
index bc58222076ac0e..f620b7077b5904 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-workgroups.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll
@@ -46,6 +46,33 @@ entry:
 attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}
 
 
+
+; Ignore if number of work groups for x dimension is 0.
+; CHECK-LABEL: {{^}}empty_max_num_workgroups_x_max:
+define amdgpu_kernel void @empty_max_num_workgroups_x_max() #5 {
+entry:
+  ret void
+}
+attributes #5 = {"amdgpu-max-num-workgroups"="4294967295,2,3"}
+
+; Ignore if number of work groups for y dimension is 0.
+; CHECK-LABEL: {{^}}empty_max_num_workgroups_y_max:
+define amdgpu_kernel void @empty_max_num_workgroups_y_max() #6 {
+entry:
+  ret void
+}
+attributes #6 = {"amdgpu-max-num-workgroups"="1,4294967295,3"}
+
+; Ignore if number of work groups for z dimension is 0.
+; CHECK-LABEL: {{^}}empty_max_num_workgroups_z_max:
+define amdgpu_kernel void @empty_max_num_workgroups_z_max() #7 {
+entry:
+  ret void
+}
+attributes #7 = {"amdgpu-max-num-workgroups"="1,2,4294967295"}
+
+
+
 ; CHECK: .amdgpu_metadata
 ; CHECK: - .args:
 ; CHECK:        .max_flat_workgroup_size: 1024
@@ -54,16 +81,25 @@ attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}
 
 ; CHECK: - .args:
 ; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_x: 0
+; CHECK-NEXT:   .max_num_workgroups_y: 2
+; CHECK-NEXT:   .max_num_workgroups_z: 3
 ; CHECK-NEXT:   .name:           empty_max_num_workgroups_x0
 ; CHECK-NEXT:   .private_segment_fixed_size: 0
 
 ; CHECK: - .args:
 ; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_x: 1
+; CHECK-NEXT:   .max_num_workgroups_y: 0
+; CHECK-NEXT:   .max_num_workgroups_z: 3
 ; CHECK-NEXT:   .name:           empty_max_num_workgroups_y0
 ; CHECK-NEXT:   .private_segment_fixed_size: 0
 
 ; CHECK: - .args:
 ; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_x: 1
+; CHECK-NEXT:   .max_num_workgroups_y: 2
+; CHECK-NEXT:   .max_num_workgroups_z: 0
 ; CHECK-NEXT:   .name:           empty_max_num_workgroups_z0
 ; CHECK-NEXT:   .private_segment_fixed_size: 0
 
@@ -82,3 +118,25 @@ attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}
 ; CHECK-NEXT:   .max_num_workgroups_z: 1024
 ; CHECK-NEXT:   .name:           empty_max_num_workgroups_1024_1024_1024
 ; CHECK-NEXT:   .private_segment_fixed_size: 0
+
+
+; CHECK: - .args:
+; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_y: 2
+; CHECK-NEXT:   .max_num_workgroups_z: 3
+; CHECK-NEXT:   .name:           empty_max_num_workgroups_x_max
+; CHECK-NEXT:   .private_segment_fixed_size: 0
+
+; CHECK: - .args:
+; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_x: 1
+; CHECK-NEXT:   .max_num_workgroups_z: 3
+; CHECK-NEXT:   .name:           empty_max_num_workgroups_y_max
+; CHECK-NEXT:   .private_segment_fixed_size: 0
+
+; CHECK: - .args:
+; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_x: 1
+; CHECK-NEXT:   .max_num_workgroups_y: 2
+; CHECK-NEXT:   .name:           empty_max_num_workgroups_z_max
+; CHECK-NEXT:   .private_segment_fixed_size: 0

shiltian · 2024-10-26T15:20:25Z

llvm/test/CodeGen/AMDGPU/attr-amdgpu-max-num-workgroups.ll

@@ -54,16 +81,25 @@ attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}

 ; CHECK: - .args:
 ; CHECK:        .max_flat_workgroup_size: 1024
+; CHECK-NEXT:   .max_num_workgroups_x: 0


What does 0 here mean? The backend guide says this must be >=1.

It doesn't say that. It states "Clang only emits this attribute when all the three numbers are >= 1." Which doesn't really make sense.

0 doesn't make sense as a value

It does say that: "The max number of launched work-groups in the X, Y, and Z dimensions. Each number must be >=1."

In trivial questions, is the hardware maximum for workgroups actually uint32_t_max in all dimensions, or is it uint32_t_max / [wave size]?

That's on the emitted directive, it's not directly documented on the IR attribute.

I think I've seen that it's lower in the y and z dimensions but I don't remember where and can't find documentation for it

arsenm · 2024-11-05T20:43:43Z

Merge activity

Nov 5, 3:43 PM EST: A user started a stack merge that includes this pull request via Graphite.
Nov 5, 3:47 PM EST: Graphite rebased this pull request as part of a merge.
Nov 5, 3:50 PM EST: A user merged this pull request with Graphite.

…groups 0 does not make sense as a value for this to be, much less the default. Also stop emitting each individual field if it is the default, rather than if any element was the default. Also fix the name of the test since it didn't exactly match the real attribute name.

shiltian · 2024-11-05T23:18:27Z

llvm/docs/AMDGPUUsage.rst

-                                             the three numbers are >= 1.
+                                             X, Y, and Z dimensions. Each number must be >= 1. Generated by the
+                                             ``amdgpu_max_num_work_groups`` CLANG attribute [CLANG-ATTR]_. Clang only
+                                             emits this attribute when all the three numbers are >= 1.


clang only emits this attribute when all the three numbers are >= 1.

Do we have sema check for this?

Should, that part isn't new

This was referenced Oct 26, 2024

AMDGPU: Propagate amdgpu-max-num-workgroups attribute #113018

Merged

AMDGPU: Mark grid size loads with range metadata #113019

Merged

arsenm mentioned this pull request Oct 26, 2024

clang/AMDGPU: Emit grid size builtins with range metadata #113038

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arsenm added the backend:AMDGPU label Oct 26, 2024 — with Graphite App

arsenm requested review from jwanggit86, krzysz00 and shiltian October 26, 2024 04:15

arsenm marked this pull request as ready for review October 26, 2024 04:15

shiltian reviewed Oct 26, 2024

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arsenm force-pushed the users/arsenm/amdgpu-default-val-amdgpu-max-num-workgroups branch from 0c10781 to 7b7992f Compare October 28, 2024 22:19

arsenm force-pushed the users/arsenm/amdgpu-default-val-amdgpu-max-num-workgroups branch from 7b7992f to ae52e0d Compare November 5, 2024 16:06

arsenm changed the base branch from main to users/arsenm/clang-amdgpu-mark-grid-size-loads-range-metadata November 5, 2024 16:06

shiltian approved these changes Nov 5, 2024

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arsenm force-pushed the users/arsenm/clang-amdgpu-mark-grid-size-loads-range-metadata branch from 6981d5a to 2e3964f Compare November 5, 2024 20:45

Base automatically changed from users/arsenm/clang-amdgpu-mark-grid-size-loads-range-metadata to main November 5, 2024 20:47

arsenm added 3 commits November 5, 2024 20:47

Update attr documentation

e15235f

Avoid invalid 0 case

fada8ca

arsenm force-pushed the users/arsenm/amdgpu-default-val-amdgpu-max-num-workgroups branch from ae52e0d to fada8ca Compare November 5, 2024 20:47

arsenm merged commit 0b40f97 into main Nov 5, 2024
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