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AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups #113751

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Merged
merged 3 commits into from
Nov 5, 2024
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AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups #113751

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f0deae2
AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-work…
arsenm Oct 26, 2024
e15235f
Update attr documentation
arsenm Oct 28, 2024
fada8ca
Avoid invalid 0 case
arsenm Oct 28, 2024
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6 changes: 3 additions & 3 deletions llvm/docs/AMDGPUUsage.rst
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Expand Up @@ -1645,9 +1645,9 @@ The AMDGPU backend supports the following LLVM IR attributes.
reduced by heuristics.

"amdgpu-max-num-workgroups"="x,y,z" Specify the maximum number of work groups for the kernel dispatch in the
X, Y, and Z dimensions. Generated by the ``amdgpu_max_num_work_groups``
CLANG attribute [CLANG-ATTR]_. Clang only emits this attribute when all
the three numbers are >= 1.
X, Y, and Z dimensions. Each number must be >= 1. Generated by the
``amdgpu_max_num_work_groups`` CLANG attribute [CLANG-ATTR]_. Clang only
emits this attribute when all the three numbers are >= 1.
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clang only emits this attribute when all the three numbers are >= 1.

Do we have sema check for this?

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Should, that part isn't new


"amdgpu-no-agpr" Indicates the function will not require allocating AGPRs. This is only
relevant on subtargets with AGPRs. The behavior is undefined if a
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17 changes: 12 additions & 5 deletions llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
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Expand Up @@ -504,14 +504,21 @@ MetadataStreamerMsgPackV4::getHSAKernelProps(const MachineFunction &MF,

Kern[".max_flat_workgroup_size"] =
Kern.getDocument()->getNode(MFI.getMaxFlatWorkGroupSize());
unsigned NumWGX = MFI.getMaxNumWorkGroupsX();
unsigned NumWGY = MFI.getMaxNumWorkGroupsY();
unsigned NumWGZ = MFI.getMaxNumWorkGroupsZ();
if (NumWGX != 0 && NumWGY != 0 && NumWGZ != 0) {

uint32_t NumWGY = MFI.getMaxNumWorkGroupsY();
uint32_t NumWGZ = MFI.getMaxNumWorkGroupsZ();
uint32_t NumWGX = MFI.getMaxNumWorkGroupsX();

// TODO: Should consider 0 invalid and reject in IR verifier.
if (NumWGX != std::numeric_limits<uint32_t>::max() && NumWGX != 0)
Kern[".max_num_workgroups_x"] = Kern.getDocument()->getNode(NumWGX);

if (NumWGY != std::numeric_limits<uint32_t>::max() && NumWGY != 0)
Kern[".max_num_workgroups_y"] = Kern.getDocument()->getNode(NumWGY);

if (NumWGZ != std::numeric_limits<uint32_t>::max() && NumWGZ != 0)
Kern[".max_num_workgroups_z"] = Kern.getDocument()->getNode(NumWGZ);
}

Kern[".sgpr_spill_count"] =
Kern.getDocument()->getNode(MFI.getNumSpilledSGPRs());
Kern[".vgpr_spill_count"] =
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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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Expand Up @@ -371,5 +371,6 @@ const AMDGPUSubtarget &AMDGPUSubtarget::get(const TargetMachine &TM, const Funct

SmallVector<unsigned>
AMDGPUSubtarget::getMaxNumWorkGroups(const Function &F) const {
return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3);
return AMDGPU::getIntegerVecAttribute(F, "amdgpu-max-num-workgroups", 3,
std::numeric_limits<uint32_t>::max());
}
7 changes: 4 additions & 3 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Expand Up @@ -1307,15 +1307,16 @@ getIntegerPairAttribute(const Function &F, StringRef Name,
}

SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
unsigned Size) {
unsigned Size,
unsigned DefaultVal) {
assert(Size > 2);
SmallVector<unsigned> Default(Size, 0);
SmallVector<unsigned> Default(Size, DefaultVal);

Attribute A = F.getFnAttribute(Name);
if (!A.isStringAttribute())
return Default;

SmallVector<unsigned> Vals(Size, 0);
SmallVector<unsigned> Vals(Size, DefaultVal);

LLVMContext &Ctx = F.getContext();

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3 changes: 2 additions & 1 deletion llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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Expand Up @@ -919,7 +919,8 @@ getIntegerPairAttribute(const Function &F, StringRef Name,
///
/// \returns false if any error occurs.
SmallVector<unsigned> getIntegerVecAttribute(const Function &F, StringRef Name,
unsigned Size);
unsigned Size,
unsigned DefaultVal = 0);

/// Represents the counter values to wait for in an s_waitcnt instruction.
///
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54 changes: 54 additions & 0 deletions ...eGen/AMDGPU/attr-amdgpu-num-workgroups.ll → .../AMDGPU/attr-amdgpu-max-num-workgroups.ll
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Expand Up @@ -46,6 +46,32 @@ entry:
attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}



; Ignore if number of work groups for x dimension is 0.
; CHECK-LABEL: {{^}}empty_max_num_workgroups_x_max:
define amdgpu_kernel void @empty_max_num_workgroups_x_max() #5 {
entry:
ret void
}
attributes #5 = {"amdgpu-max-num-workgroups"="4294967295,2,3"}

; Ignore if number of work groups for y dimension is 0.
; CHECK-LABEL: {{^}}empty_max_num_workgroups_y_max:
define amdgpu_kernel void @empty_max_num_workgroups_y_max() #6 {
entry:
ret void
}
attributes #6 = {"amdgpu-max-num-workgroups"="1,4294967295,3"}

; Ignore if number of work groups for z dimension is 0.
; CHECK-LABEL: {{^}}empty_max_num_workgroups_z_max:
define amdgpu_kernel void @empty_max_num_workgroups_z_max() #7 {
entry:
ret void
}
attributes #7 = {"amdgpu-max-num-workgroups"="1,2,4294967295"}


; CHECK: .amdgpu_metadata
; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
Expand All @@ -54,16 +80,22 @@ attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}

; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
; CHECK-NEXT: .max_num_workgroups_y: 2
; CHECK-NEXT: .max_num_workgroups_z: 3
; CHECK-NEXT: .name: empty_max_num_workgroups_x0
; CHECK-NEXT: .private_segment_fixed_size: 0

; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
; CHECK-NEXT: .max_num_workgroups_x: 1
; CHECK-NEXT: .max_num_workgroups_z: 3
; CHECK-NEXT: .name: empty_max_num_workgroups_y0
; CHECK-NEXT: .private_segment_fixed_size: 0

; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
; CHECK-NEXT: .max_num_workgroups_x: 1
; CHECK-NEXT: .max_num_workgroups_y: 2
; CHECK-NEXT: .name: empty_max_num_workgroups_z0
; CHECK-NEXT: .private_segment_fixed_size: 0

Expand All @@ -82,3 +114,25 @@ attributes #4 = {"amdgpu-max-num-workgroups"="1024,1024,1024"}
; CHECK-NEXT: .max_num_workgroups_z: 1024
; CHECK-NEXT: .name: empty_max_num_workgroups_1024_1024_1024
; CHECK-NEXT: .private_segment_fixed_size: 0


; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
; CHECK-NEXT: .max_num_workgroups_y: 2
; CHECK-NEXT: .max_num_workgroups_z: 3
; CHECK-NEXT: .name: empty_max_num_workgroups_x_max
; CHECK-NEXT: .private_segment_fixed_size: 0

; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
; CHECK-NEXT: .max_num_workgroups_x: 1
; CHECK-NEXT: .max_num_workgroups_z: 3
; CHECK-NEXT: .name: empty_max_num_workgroups_y_max
; CHECK-NEXT: .private_segment_fixed_size: 0

; CHECK: - .args:
; CHECK: .max_flat_workgroup_size: 1024
; CHECK-NEXT: .max_num_workgroups_x: 1
; CHECK-NEXT: .max_num_workgroups_y: 2
; CHECK-NEXT: .name: empty_max_num_workgroups_z_max
; CHECK-NEXT: .private_segment_fixed_size: 0
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