[GlobalISel] Add G_STEP_VECTOR instruction #115598

tschuett · 2024-11-09T09:54:25Z

aka llvm.stepvector Intrinsic

llvmbot · 2024-11-09T09:54:58Z

@llvm/pr-subscribers-llvm-support
@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-aarch64

Author: Thorsten Schütt (tschuett)

Changes

aka llvm.stepvector Intrinsic

Full diff: https://github.com/llvm/llvm-project/pull/115598.diff

9 Files Affected:

(modified) llvm/docs/GlobalISel/GenericOpcode.rst (+16)
(modified) llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h (+10)
(modified) llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (+23)
(modified) llvm/include/llvm/Support/TargetOpcodes.def (+3)
(modified) llvm/include/llvm/Target/GenericOpcodes.td (+7)
(modified) llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp (+15-1)
(modified) llvm/lib/CodeGen/MachineVerifier.cpp (+30)
(modified) llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (+3)
(added) llvm/test/MachineVerifier/test_step-vector.mir (+29)

diff --git a/llvm/docs/GlobalISel/GenericOpcode.rst b/llvm/docs/GlobalISel/GenericOpcode.rst
index 8920530dc3f1a1..b360d4ba35b80e 100644
--- a/llvm/docs/GlobalISel/GenericOpcode.rst
+++ b/llvm/docs/GlobalISel/GenericOpcode.rst
@@ -753,6 +753,22 @@ The type of the operand must be equal to or larger than the vector element
 type. If the operand is larger than the vector element type, the scalar is
 implicitly truncated to the vector element type.
 
+G_STEP_VECTOR
+^^^^^^^^^^^^^^^^
+
+Create a scalable vector where all lanes are linear sequences starting at 0
+with a given unsigned step.
+
+The type of the operand must be equal to the vector element type.
+
+.. code-block::
+
+  %0:_(<vscale x 2 x s64>) = G_STEP_VECTOR i64 4
+
+  %1:_(<vscale x s32>) = G_STEP_VECTOR i32 4
+
+  0, 1*Step, 2*Step, 3*Step, 4*Step, ...
+
 G_VECTOR_COMPRESS
 ^^^^^^^^^^^^^^^^^
 
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index cd7ebcf54c9e1e..2c507633e1771d 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -906,6 +906,16 @@ class GVScale : public GenericMachineInstr {
   };
 };
 
+/// Represents a step vector.
+class GStepVector : public GenericMachineInstr {
+public:
+  APInt getStep() const { return getOperand(1).getCImm()->getValue(); }
+
+  static bool classof(const MachineInstr *MI) {
+    return MI->getOpcode() == TargetOpcode::G_STEP_VECTOR;
+  };
+};
+
 /// Represents an integer subtraction.
 class GSub : public GIntBinOp {
 public:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index a38dd34a17097a..37ea9c4b9a124f 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1172,6 +1172,29 @@ class MachineIRBuilder {
   MachineInstrBuilder buildInsert(const DstOp &Res, const SrcOp &Src,
                                   const SrcOp &Op, unsigned Index);
 
+  /// Build and insert \p Res = G_STEP_VECTOR \p Step
+  ///
+  /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
+  /// into \p Res.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res must be a generic virtual register with scalar type.
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildStepVector(const DstOp &Res,
+                                      const ConstantInt &Step);
+
+  /// Build and insert \p Res = G_STEP_VECTOR \p Step
+  ///
+  /// G_STEP_VECTOR returns a scalable vector of linear sequence of step \p Step
+  /// into \p Res.
+  ///
+  /// \pre setBasicBlock or setMI must have been called.
+  /// \pre \p Res must be a generic virtual register with scalar type.
+  ///
+  /// \return a MachineInstrBuilder for the newly created instruction.
+  MachineInstrBuilder buildStepVector(const DstOp &Res, const APInt &Step);
+
   /// Build and insert \p Res = G_VSCALE \p MinElts
   ///
   /// G_VSCALE puts the value of the runtime vscale multiplied by \p MinElts
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index 0c4c6ccd5c568e..17987935ed3cf4 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -776,6 +776,9 @@ HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
 /// Generic splatvector.
 HANDLE_TARGET_OPCODE(G_SPLAT_VECTOR)
 
+/// Generic stepvector.
+HANDLE_TARGET_OPCODE(G_STEP_VECTOR)
+
 /// Generic masked compress.
 HANDLE_TARGET_OPCODE(G_VECTOR_COMPRESS)
 
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 62bb9789afe5d2..60606db078b374 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1590,6 +1590,13 @@ def G_SPLAT_VECTOR: GenericInstruction {
   let hasSideEffects = false;
 }
 
+// Generic stepvector.
+def G_STEP_VECTOR: GenericInstruction {
+  let OutOperandList = (outs type0:$dst);
+  let InOperandList = (ins unknown:$step);
+  let hasSideEffects = false;
+}
+
 // Generic masked compress.
 def G_VECTOR_COMPRESS: GenericInstruction {
   let OutOperandList = (outs type0:$dst);
diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
index 02dbe781babdba..a8836eef0c1813 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -809,9 +809,23 @@ MachineInstrBuilder MachineIRBuilder::buildInsert(const DstOp &Res,
   return buildInstr(TargetOpcode::G_INSERT, Res, {Src, Op, uint64_t(Index)});
 }
 
+MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
+                                                      const APInt &Step) {
+  ConstantInt *CI = ConstantInt::get(getMF().getFunction().getContext(), Step);
+  return buildStepVector(Res, *CI);
+}
+
+MachineInstrBuilder MachineIRBuilder::buildStepVector(const DstOp &Res,
+                                                      const ConstantInt &Step) {
+  auto StepVector = buildInstr(TargetOpcode::G_STEP_VECTOR);
+  StepVector->setDebugLoc(DebugLoc());
+  Res.addDefToMIB(*getMRI(), StepVector);
+  StepVector.addCImm(&Step);
+  return StepVector;
+}
+
 MachineInstrBuilder MachineIRBuilder::buildVScale(const DstOp &Res,
                                                   unsigned MinElts) {
-
   auto IntN = IntegerType::get(getMF().getFunction().getContext(),
                                Res.getLLTTy(*getMRI()).getScalarSizeInBits());
   ConstantInt *CI = ConstantInt::get(IntN, MinElts);
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index e2c09fe25d55cd..b13c6abb26ccd1 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1729,6 +1729,36 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
     }
     break;
   }
+  case TargetOpcode::G_STEP_VECTOR: {
+    if (!MI->getOperand(1).isCImm()) {
+      report("operand must be cimm", MI);
+      break;
+    }
+
+    if (!MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
+      report("step must be >= 0", MI);
+      break;
+    }
+
+    LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
+    if (!DstTy.isScalableVector()) {
+      report("Destination type must be a scalable vector", MI);
+      break;
+    }
+
+    // <vscale x 2 x p0>
+    if (!DstTy.getElementType().isScalar()) {
+      report("Destination element type must be scalar", MI);
+      break;
+    }
+
+    if (MI->getOperand(1).getCImm()->getBitWidth() !=
+        DstTy.getElementType().getScalarSizeInBits()) {
+      report("step bitwidth differs from result type element bitwidth", MI);
+      break;
+    }
+    break;
+  }
   case TargetOpcode::G_INSERT_SUBVECTOR: {
     const MachineOperand &Src0Op = MI->getOperand(1);
     if (!Src0Op.isReg()) {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 6be99d0088f1cb..f4c702c50ca774 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -665,6 +665,9 @@
 # DEBUG-NEXT: G_SPLAT_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_STEP_VECTOR (opcode 236): 2 type indices, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_VECTOR_COMPRESS (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/MachineVerifier/test_step-vector.mir b/llvm/test/MachineVerifier/test_step-vector.mir
new file mode 100644
index 00000000000000..9065e7fdf39d39
--- /dev/null
+++ b/llvm/test/MachineVerifier/test_step-vector.mir
@@ -0,0 +1,29 @@
+# RUN: not --crash llc -verify-machineinstrs -mtriple=arm64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name:            g_step_vector
+body: |
+  bb.0:
+
+  %0:_(s32) = G_CONSTANT i32 4
+
+  ; CHECK: operand must be cimm
+  %1:_(s32) = G_STEP_VECTOR %0
+
+  ; CHECK: step must be >= 0
+  %2:_(s32) = G_STEP_VECTOR i32 -1
+
+  ; CHECK: Destination type must be a scalable vector
+  %3:_(<4 x s64>) = G_STEP_VECTOR i32 5
+
+  ; CHECK: Destination element type must be scalar
+  %4:_(<vscale x 4 x p0>) = G_STEP_VECTOR i32 9
+
+  ; CHECK: step bitwidth differs from result type element bitwidth
+  %6:_(<vscale x 2 x s33>) = G_STEP_VECTOR i32 56
+
+  %7:_(<vscale x 2 x s128>) = G_STEP_VECTOR i128 79
+
+...
+

aemerson · 2024-11-09T22:14:07Z

llvm/docs/GlobalISel/GenericOpcode.rst

+G_STEP_VECTOR
+^^^^^^^^^^^^^
+
+Create a scalable vector where all lanes are linear sequences starting at 0
+with a given unsigned step.
+
+The type of the operand must be equal to the vector element type.


The equivalent node for SelectionDAG also specifies the wrapping behavior.

Should also document the restriction on scalable vector dest type that the verifier is enforcing.

aemerson · 2024-11-09T22:16:04Z

llvm/lib/CodeGen/MachineVerifier.cpp

+    if (!MI->getOperand(1).getCImm()->getValue().isStrictlyPositive()) {
+      report("step must be >= 0", MI);
+      break;
+    }


If the step is unsigned as the doc specifies, then does this still make sense?

The step is ConstantInt or APInt. Neither enforces the behaviour.

For step=0, we create a step vector of all zeros. The canonical representation is a splat vector of zeros. It would loose the stepping property.

So the message should say > 0 not >= 0?

aka llvm.stepvector Intrinsic

aemerson

LGTM with some minor comments.

aemerson · 2024-11-10T22:20:24Z

llvm/docs/GlobalISel/GenericOpcode.rst

+
+The type of the operand must be equal to the vector element type. Arithmetic
+is performed modulo the bitwidth of the element. The step must be > 0.
+Otherwise the vector is zero. The canonical representation is a splat vector


This sentence doesn't need to be here.

aemerson · 2024-11-10T22:23:24Z

llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h

+class GStepVector : public GenericMachineInstr {
+public:
+  APInt getStep() const { return getOperand(1).getCImm()->getValue(); }
+


Maybe also add a variant to return a uint64_t for convenience?

I replaced the APInt by an uint64_t. The step is unsigned.

aka llvm.stepvector Intrinsic

tschuett requested review from aemerson, arsenm, michaelmaitland and topperc November 9, 2024 09:54

llvmbot added backend:AArch64 llvm:globalisel llvm:support labels Nov 9, 2024

aemerson reviewed Nov 9, 2024

View reviewed changes

tschuett force-pushed the gisel-step-vector branch from bb5ed03 to 6c166f2 Compare November 10, 2024 09:24

Thorsten Schütt added 9 commits November 10, 2024 17:26

[GlobalISel] Add G_STEP_VECTOR instruction

00bca23

aka llvm.stepvector Intrinsic

small fixes

1593236

white space

5e6deac

fix validation

4ec7442

address review comments

68d0a39

docs + >= -> >

04f916f

fix type

5cfd041

docs

f38c31d

more docs

7a26409

tschuett force-pushed the gisel-step-vector branch from 000063d to 7a26409 Compare November 10, 2024 16:26

fix riscv legalizer validation

3f47c37

aemerson approved these changes Nov 10, 2024

View reviewed changes

Thorsten Schütt added 2 commits November 11, 2024 07:05

address review comments

f95d39b

unmerge

c3a674e

tschuett merged commit a5d09f4 into llvm:main Nov 11, 2024
9 checks passed

tschuett deleted the gisel-step-vector branch November 11, 2024 09:45

Groverkss pushed a commit to iree-org/llvm-project that referenced this pull request Nov 15, 2024

[GlobalISel] Add G_STEP_VECTOR instruction (llvm#115598)

96fe3b8

aka llvm.stepvector Intrinsic

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