[AArch64][GlobalISel] Do not create LIFETIME instructions in functions. #115669
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For the same reason that we do not translate lifetime markers in a -O0, we should not translate them for optnone functions too.
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@llvm/pr-subscribers-backend-aarch64 Author: David Green (davemgreen) ChangesFor the same reason that we do not translate lifetime markers in a -O0, we should not translate them for optnone functions too. Full diff: https://github.com/llvm/llvm-project/pull/115669.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 349c35b3781d16..056f4f41ffca79 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2166,7 +2166,8 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::lifetime_start:
case Intrinsic::lifetime_end: {
// No stack colouring in O0, discard region information.
- if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None)
+ if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None ||
+ MF->getFunction().hasOptNone())
return true;
unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index ed7bcff5160f81..7a67cf3fd4c942 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1477,6 +1477,20 @@ define void @test_lifetime_intrin() {
ret void
}
+define void @test_lifetime_intrin_optnone() optnone noinline {
+; CHECK-LABEL: name: test_lifetime_intrin_optnone
+; CHECK: RET_ReallyLR
+; O3-LABEL: name: test_lifetime_intrin_optnone
+; O3: {{%[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.slot
+; O3-NEXT: G_STORE
+; O3-NEXT: RET_ReallyLR
+ %slot = alloca i8, i32 4
+ call void @llvm.lifetime.start.p0(i64 0, ptr %slot)
+ store volatile i8 10, ptr %slot
+ call void @llvm.lifetime.end.p0(i64 0, ptr %slot)
+ ret void
+}
+
define void @test_load_store_atomics(ptr %addr) {
; CHECK-LABEL: name: test_load_store_atomics
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
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@llvm/pr-subscribers-llvm-globalisel Author: David Green (davemgreen) ChangesFor the same reason that we do not translate lifetime markers in a -O0, we should not translate them for optnone functions too. Full diff: https://github.com/llvm/llvm-project/pull/115669.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 349c35b3781d16..056f4f41ffca79 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2166,7 +2166,8 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::lifetime_start:
case Intrinsic::lifetime_end: {
// No stack colouring in O0, discard region information.
- if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None)
+ if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None ||
+ MF->getFunction().hasOptNone())
return true;
unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
index ed7bcff5160f81..7a67cf3fd4c942 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
@@ -1477,6 +1477,20 @@ define void @test_lifetime_intrin() {
ret void
}
+define void @test_lifetime_intrin_optnone() optnone noinline {
+; CHECK-LABEL: name: test_lifetime_intrin_optnone
+; CHECK: RET_ReallyLR
+; O3-LABEL: name: test_lifetime_intrin_optnone
+; O3: {{%[0-9]+}}:_(p0) = G_FRAME_INDEX %stack.0.slot
+; O3-NEXT: G_STORE
+; O3-NEXT: RET_ReallyLR
+ %slot = alloca i8, i32 4
+ call void @llvm.lifetime.start.p0(i64 0, ptr %slot)
+ store volatile i8 10, ptr %slot
+ call void @llvm.lifetime.end.p0(i64 0, ptr %slot)
+ ret void
+}
+
define void @test_load_store_atomics(ptr %addr) {
; CHECK-LABEL: name: test_load_store_atomics
; CHECK: [[ADDR:%[0-9]+]]:_(p0) = COPY $x0
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aemerson
approved these changes
Nov 10, 2024
arsenm
reviewed
Nov 11, 2024
| @@ -2166,7 +2166,8 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, | |||
| case Intrinsic::lifetime_start: | |||
| case Intrinsic::lifetime_end: { | |||
| // No stack colouring in O0, discard region information. | |||
| if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None) | |||
| if (MF->getTarget().getOptLevel() == CodeGenOptLevel::None || | |||
| MF->getFunction().hasOptNone()) | |||
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The DAG doesn't check this, fix both together?
There was a problem hiding this comment.
It looks like DAG goes via OptLevelChanger, which sets the OptLevel and resets it after handling the function. (And forces into using fast-isel, even if we would not usually use it).
Groverkss
pushed a commit
to iree-org/llvm-project
that referenced
this pull request
Nov 15, 2024
…s. (llvm#115669) For the same reason that we do not translate lifetime markers in a -O0, we should not translate them for optnone functions too.
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For the same reason that we do not translate lifetime markers in a -O0, we should not translate them for optnone functions too.