[RISCV] Add mvendorid/marchid/mimpid to CPU definitions #116202
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) ChangesWe can get these information via This can be used to implement Full diff: https://github.com/llvm/llvm-project/pull/116202.diff 4 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e52a856183678a..84fa25f48ec61a 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -49,6 +49,9 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
+ int MVendorID = 0;
+ int MArchID = 0;
+ int MImpID = 0;
}
class RISCVTuneProcessorModel<string n,
@@ -435,7 +438,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion,
- TuneLDADDFusion]>;
+ TuneLDADDFusion]> {
+ let MVendorID = 0x61f;
+ let MArchID = 0x8000000000010000;
+ let MImpID = 0x111;
+}
def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
XiangShanNanHuModel,
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 49a35bfcf4b9b7..62fbd3458112e2 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -22,7 +22,7 @@ namespace RISCV {
enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN) \
+ FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
@@ -33,13 +33,24 @@ struct CPUInfo {
StringLiteral DefaultMarch;
bool FastScalarUnalignedAccess;
bool FastVectorUnalignedAccess;
+ uint32_t MVendorID;
+ uint64_t MArchID;
+ uint64_t MImpID;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};
constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
- FAST_VECTOR_UNALIGN) \
- {NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
+ FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
+ { \
+ NAME, \
+ DEFAULT_MARCH, \
+ FAST_SCALAR_UNALIGN, \
+ FAST_VECTOR_UNALIGN, \
+ MVENDORID, \
+ MARCHID, \
+ MIMPID, \
+ },
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};
diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td
index c071cfd731cb52..3267c282cffda7 100644
--- a/llvm/test/TableGen/riscv-target-def.td
+++ b/llvm/test/TableGen/riscv-target-def.td
@@ -81,6 +81,9 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
+ int MVendorID = 0;
+ int MArchID = 0;
+ int MImpID = 0;
}
class RISCVTuneProcessorModel<string n,
@@ -160,13 +163,13 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK: #endif // GET_SUPPORTED_PROFILES
// CHECK: #ifndef PROC
-// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
+// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
// CHECK-NEXT: #endif
-// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
-// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
-// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
-// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
+// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
+// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
+// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x00000000, 0x00000000)
+// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK: #undef PROC
diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
index 39211aab6f2d1e..4ab45cfc09f133 100644
--- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
@@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/DenseSet.h"
+#include "llvm/Support/Format.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -166,7 +167,7 @@ static void emitRISCVProfiles(const RecordKeeper &Records, raw_ostream &OS) {
static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
<< "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN"
- << ", FAST_VECTOR_UNALIGN)\n"
+ << ", FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)\n"
<< "#endif\n\n";
// Iterate on all definition records.
@@ -182,6 +183,10 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
return Feature->getValueAsString("Name") == "unaligned-vector-mem";
});
+ bool IsRV64 = any_of(Features, [&](auto &Feature) {
+ return Feature->getValueAsString("Name") == "64bit";
+ });
+
OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
<< "\"}, {\"";
@@ -192,8 +197,17 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
printMArch(OS, Features);
else
OS << MArch;
+
+ uint32_t MVendorID = Rec->getValueAsInt("MVendorID");
+ uint64_t MArchID = Rec->getValueAsInt("MArchID");
+ uint64_t MImpID = Rec->getValueAsInt("MImpID");
+
OS << "\"}, " << FastScalarUnalignedAccess << ", "
- << FastVectorUnalignedAccess << ")\n";
+ << FastVectorUnalignedAccess;
+ OS << ", " << format_hex(MVendorID, 10);
+ OS << ", " << format_hex(MArchID, IsRV64 ? 18 : 10);
+ OS << ", " << format_hex(MImpID, IsRV64 ? 18 : 10);
+ OS << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
|
wangpc-pp
commented
Nov 14, 2024
| @@ -435,7 +438,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", | |||
| TuneZExtHFusion, | |||
| TuneZExtWFusion, | |||
| TuneShiftedZExtWFusion, | |||
| TuneLDADDFusion]>; | |||
| TuneLDADDFusion]> { | |||
| let MVendorID = 0x61f; | |||
There was a problem hiding this comment.
lenary
approved these changes
Nov 14, 2024
dtcxzyw
reviewed
Nov 14, 2024
topperc
reviewed
Nov 18, 2024
We can get these information via `sys_riscv_hwprobe`. This can be used to implement `__builtin_cpu_is`.
wangpc-pp
force-pushed
the
main-riscv-cpu-vendor-id
branch
from
2e4471a to
1572068
Compare
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/163/builds/9471 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/174/builds/8896 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/181/builds/9090 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/30/builds/10823 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/3/builds/8076 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/144/builds/12271 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/180/builds/8857 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/8982 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/123/builds/9912 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/140/builds/11505 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/133/builds/7262 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/8984 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/27/builds/2413 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/9096 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/160/builds/8859 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/195/builds/1410 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/130/builds/6550 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/116/builds/6728 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/8982 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/8/builds/7504 Here is the relevant piece of the build log for the reference |
wangpc-pp
added a commit
that referenced
this pull request
Nov 22, 2024
We have defined `__riscv_cpu_model` variable in #101449. It contains `mvendorid`, `marchid` and `mimpid` fields which are read via system call `sys_riscv_hwprobe`. We can support `__builtin_cpu_is` via comparing values in compiler's CPU definitions and `__riscv_cpu_model`. This depends on #116202. Reviewers: lenary, BeMg, kito-cheng, preames, lukel97 Reviewed By: lenary Pull Request: #116231
|
b36fcf4 should fix the error, sorry for the noise. |
metaflow
added a commit
that referenced
this pull request
Nov 22, 2024
)" chain This reverts commit b36fcf4. This reverts commit c11b6b1. This reverts commit 775148f. multiple bot build breakages, e.g. https://lab.llvm.org/buildbot/#/builders/3/builds/8076
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/33/builds/6998 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/92/builds/10191 Here is the relevant piece of the build log for the reference |
wangpc-pp
added a commit
that referenced
this pull request
Nov 22, 2024
We can get these information via `sys_riscv_hwprobe`. This can be used to implement `__builtin_cpu_is`.
wangpc-pp
added a commit
that referenced
this pull request
Nov 22, 2024
We have defined `__riscv_cpu_model` variable in #101449. It contains `mvendorid`, `marchid` and `mimpid` fields which are read via system call `sys_riscv_hwprobe`. We can support `__builtin_cpu_is` via comparing values in compiler's CPU definitions and `__riscv_cpu_model`. This depends on #116202. Reviewers: lenary, BeMg, kito-cheng, preames, lukel97 Reviewed By: lenary Pull Request: #116231
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
We can get these information via
sys_riscv_hwprobe.This can be used to implement
__builtin_cpu_is.