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[RISCV] Add mvendorid/marchid/mimpid to CPU definitions #116202

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Merged
merged 4 commits into from
Nov 22, 2024
+57 −20
Merged

[RISCV] Add mvendorid/marchid/mimpid to CPU definitions #116202

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23c84c3
[RISCV] Add mvendorid/marchid/mimpid to CPU definitions
wangpc-pp Nov 14, 2024
2e26b90
Add spacemit-x60
wangpc-pp Nov 15, 2024
721a622
Emit 64bits literal imm
wangpc-pp Nov 15, 2024
1572068
Move CPUInfo to header and add CPUModel struct
wangpc-pp Nov 15, 2024
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15 changes: 15 additions & 0 deletions llvm/include/llvm/TargetParser/RISCVTargetParser.h
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,21 @@ struct RISCVExtensionBitmask {
};
} // namespace RISCVExtensionBitmaskTable

struct CPUModel {
uint32_t MVendorID;
uint64_t MArchID;
uint64_t MImpID;
};

struct CPUInfo {
StringLiteral Name;
StringLiteral DefaultMarch;
bool FastScalarUnalignedAccess;
bool FastVectorUnalignedAccess;
CPUModel CPUModel;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};

// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;

Expand Down
15 changes: 13 additions & 2 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -49,6 +49,9 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
int MVendorID = 0;
int MArchID = 0;
int MImpID = 0;
}

class RISCVTuneProcessorModel<string n,
Expand Down Expand Up @@ -457,7 +460,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion,
TuneLDADDFusion]>;
TuneLDADDFusion]> {
let MVendorID = 0x61f;
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This is from https://github.com/qemu/qemu/blob/master/target/riscv/cpu_vendorid.h.

let MArchID = 0x8000000000010000;
let MImpID = 0x111;
}

def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
XiangShanNanHuModel,
Expand Down Expand Up @@ -503,7 +510,11 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
[TuneDLenFactor2,
TuneOptimizedNF2SegmentLoadStore,
TuneOptimizedNF3SegmentLoadStore,
TuneOptimizedNF4SegmentLoadStore]>;
TuneOptimizedNF4SegmentLoadStore]> {
let MVendorID = 0x710;
let MArchID = 0x8000000058000001;
let MImpID = 0x1000000049772200;
}

def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
NoSchedModel,
Expand Down
20 changes: 9 additions & 11 deletions llvm/lib/TargetParser/RISCVTargetParser.cpp
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Expand Up @@ -21,24 +21,22 @@ namespace RISCV {

enum CPUKind : unsigned {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
FAST_VECTOR_UNALIGN) \
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
CK_##ENUM,
#define TUNE_PROC(ENUM, NAME) CK_##ENUM,
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};

struct CPUInfo {
StringLiteral Name;
StringLiteral DefaultMarch;
bool FastScalarUnalignedAccess;
bool FastVectorUnalignedAccess;
bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
};

constexpr CPUInfo RISCVCPUInfo[] = {
#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, \
FAST_VECTOR_UNALIGN) \
{NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN},
FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID) \
{ \
NAME, \
DEFAULT_MARCH, \
FAST_SCALAR_UNALIGN, \
FAST_VECTOR_UNALIGN, \
{MVENDORID, MARCHID, MIMPID}, \
},
#include "llvm/TargetParser/RISCVTargetParserDef.inc"
};

Expand Down
13 changes: 8 additions & 5 deletions llvm/test/TableGen/riscv-target-def.td
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Expand Up @@ -81,6 +81,9 @@ class RISCVProcessorModel<string n,
string default_march = "">
: ProcessorModel<n, m, f, tunef> {
string DefaultMarch = default_march;
int MVendorID = 0;
int MArchID = 0;
int MImpID = 0;
}

class RISCVTuneProcessorModel<string n,
Expand Down Expand Up @@ -160,13 +163,13 @@ def ROCKET : RISCVTuneProcessorModel<"rocket",
// CHECK: #endif // GET_SUPPORTED_PROFILES

// CHECK: #ifndef PROC
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN)
// CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN, FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)
// CHECK-NEXT: #endif

// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0)
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0)
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0)
// CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)
// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0, 0, 0x00000000, 0x0000000000000000, 0x0000000000000000)

// CHECK: #undef PROC

Expand Down
14 changes: 12 additions & 2 deletions llvm/utils/TableGen/RISCVTargetDefEmitter.cpp
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Expand Up @@ -12,6 +12,7 @@
//===----------------------------------------------------------------------===//

#include "llvm/ADT/DenseSet.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/RISCVISAUtils.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
Expand Down Expand Up @@ -166,7 +167,7 @@ static void emitRISCVProfiles(const RecordKeeper &Records, raw_ostream &OS) {
static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
OS << "#ifndef PROC\n"
<< "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_SCALAR_UNALIGN"
<< ", FAST_VECTOR_UNALIGN)\n"
<< ", FAST_VECTOR_UNALIGN, MVENDORID, MARCHID, MIMPID)\n"
<< "#endif\n\n";

// Iterate on all definition records.
Expand All @@ -192,8 +193,17 @@ static void emitRISCVProcs(const RecordKeeper &RK, raw_ostream &OS) {
printMArch(OS, Features);
else
OS << MArch;

uint32_t MVendorID = Rec->getValueAsInt("MVendorID");
uint64_t MArchID = Rec->getValueAsInt("MArchID");
uint64_t MImpID = Rec->getValueAsInt("MImpID");

OS << "\"}, " << FastScalarUnalignedAccess << ", "
<< FastVectorUnalignedAccess << ")\n";
<< FastVectorUnalignedAccess;
OS << ", " << format_hex(MVendorID, 10);
OS << ", " << format_hex(MArchID, 18);
OS << ", " << format_hex(MImpID, 18);
OS << ")\n";
}
OS << "\n#undef PROC\n";
OS << "\n";
Expand Down
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