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Nov 18, 2024
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Reland "[X86] Support -march=diamondrapids (#113881)" #116564

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2 changes: 2 additions & 0 deletions clang/docs/ReleaseNotes.rst
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Expand Up @@ -769,6 +769,8 @@ X86 Support
- Support ISA of ``AMX-TF32``.
- Support ISA of ``MOVRS``.

- Supported ``-march/tune=diamondrapids``

Arm and AArch64 Support
^^^^^^^^^^^^^^^^^^^^^^^

Expand Down
2 changes: 2 additions & 0 deletions clang/lib/Basic/Targets/X86.cpp
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Expand Up @@ -667,6 +667,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
case CK_GraniterapidsD:
case CK_Emeraldrapids:
case CK_Clearwaterforest:
case CK_Diamondrapids:
// FIXME: Historically, we defined this legacy name, it would be nice to
// remove it at some point. We've never exposed fine-grained names for
// recent primary x86 CPUs, and we should keep it that way.
Expand Down Expand Up @@ -1651,6 +1652,7 @@ std::optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
case CK_GraniterapidsD:
case CK_Emeraldrapids:
case CK_Clearwaterforest:
case CK_Diamondrapids:
case CK_KNL:
case CK_KNM:
// K7
Expand Down
1 change: 1 addition & 0 deletions clang/test/CodeGen/attr-cpuspecific-cpus.c
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Expand Up @@ -43,6 +43,7 @@ ATTR(cpu_specific(icelake_client)) void CPU(void){}
ATTR(cpu_specific(tigerlake)) void CPU(void){}
ATTR(cpu_specific(alderlake)) void CPU(void){}
ATTR(cpu_specific(sapphirerapids)) void CPU(void){}
ATTR(cpu_specific(diamondrapids)) void CPU(void){}

// ALIAS CPUs
ATTR(cpu_specific(pentium_iii_no_xmm_regs)) void CPU0(void){}
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1 change: 1 addition & 0 deletions clang/test/CodeGen/attr-target-mv.c
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Expand Up @@ -29,6 +29,7 @@ int __attribute__((target("arch=lunarlake"))) foo(void) {return 23;}
int __attribute__((target("arch=gracemont"))) foo(void) {return 24;}
int __attribute__((target("arch=pantherlake"))) foo(void) {return 25;}
int __attribute__((target("arch=clearwaterforest"))) foo(void) {return 26;}
int __attribute__((target("arch=diamondrapids"))) foo(void) {return 27;}
int __attribute__((target("default"))) foo(void) { return 2; }

int bar(void) {
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1 change: 1 addition & 0 deletions clang/test/CodeGen/target-builtin-noerror.c
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Expand Up @@ -209,4 +209,5 @@ void verifycpustrings(void) {
(void)__builtin_cpu_is("znver3");
(void)__builtin_cpu_is("znver4");
(void)__builtin_cpu_is("znver5");
(void)__builtin_cpu_is("diamondrapids");
}
4 changes: 4 additions & 0 deletions clang/test/Driver/x86-march.c
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Expand Up @@ -120,6 +120,10 @@
// RUN: | FileCheck %s -check-prefix=clearwaterforest
// clearwaterforest: "-target-cpu" "clearwaterforest"
//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=diamondrapids 2>&1 \
// RUN: | FileCheck %s -check-prefix=diamondrapids
// diamondrapids: "-target-cpu" "diamondrapids"
//
// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=lakemont 2>&1 \
// RUN: | FileCheck %s -check-prefix=lakemont
// lakemont: "-target-cpu" "lakemont"
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4 changes: 4 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/x86.c
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Expand Up @@ -69,6 +69,7 @@
// X86-SAME: {{^}}, graniterapids-d
// X86-SAME: {{^}}, emeraldrapids
// X86-SAME: {{^}}, clearwaterforest
// X86-SAME: {{^}}, diamondrapids
// X86-SAME: {{^}}, knl
// X86-SAME: {{^}}, knm
// X86-SAME: {{^}}, lakemont
Expand Down Expand Up @@ -155,6 +156,7 @@
// X86_64-SAME: {{^}}, graniterapids-d
// X86_64-SAME: {{^}}, emeraldrapids
// X86_64-SAME: {{^}}, clearwaterforest
// X86_64-SAME: {{^}}, diamondrapids
// X86_64-SAME: {{^}}, knl
// X86_64-SAME: {{^}}, knm
// X86_64-SAME: {{^}}, k8
Expand Down Expand Up @@ -250,6 +252,7 @@
// TUNE_X86-SAME: {{^}}, graniterapids-d
// TUNE_X86-SAME: {{^}}, emeraldrapids
// TUNE_X86-SAME: {{^}}, clearwaterforest
// TUNE_X86-SAME: {{^}}, diamondrapids
// TUNE_X86-SAME: {{^}}, knl
// TUNE_X86-SAME: {{^}}, knm
// TUNE_X86-SAME: {{^}}, lakemont
Expand Down Expand Up @@ -352,6 +355,7 @@
// TUNE_X86_64-SAME: {{^}}, graniterapids-d
// TUNE_X86_64-SAME: {{^}}, emeraldrapids
// TUNE_X86_64-SAME: {{^}}, clearwaterforest
// TUNE_X86_64-SAME: {{^}}, diamondrapids
// TUNE_X86_64-SAME: {{^}}, knl
// TUNE_X86_64-SAME: {{^}}, knm
// TUNE_X86_64-SAME: {{^}}, lakemont
Expand Down
54 changes: 54 additions & 0 deletions clang/test/Preprocessor/predefined-arch-macros.c
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Expand Up @@ -1867,13 +1867,23 @@
// RUN: %clang -march=graniterapids-d -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32
// RUN: %clang -march=diamondrapids -m32 -E -dM %s -o - 2>&1 \
// RUN: --target=i386 \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M32,CHECK_GNRD_M32,CHECK_DMR_M32
// CHECK_GNR_M32: #define __AES__ 1
// CHECK_DMR_M32: #define __AMX_AVX512__ 1
// CHECK_GNR_M32: #define __AMX_BF16__ 1
// CHECK_GNR_M32-NOT: #define __AMX_COMPLEX__ 1
// CHECK_GNRD_M32: #define __AMX_COMPLEX__ 1
// CHECK_GNR_M32: #define __AMX_FP16__ 1
// CHECK_DMR_M32: #define __AMX_FP8__ 1
// CHECK_GNR_M32: #define __AMX_INT8__ 1
// CHECK_DMR_M32: #define __AMX_MOVRS__ 1
// CHECK_DMR_M32: #define __AMX_TF32__ 1
// CHECK_GNR_M32: #define __AMX_TILE__ 1
// CHECK_DMR_M32: #define __AMX_TRANSPOSE__ 1
// CHECK_DMR_M32: #define __AVX10_2_512__ 1
// CHECK_DMR_M32: #define __AVX10_2__ 1
// CHECK_GNR_M32: #define __AVX2__ 1
// CHECK_GNR_M32: #define __AVX512BF16__ 1
// CHECK_GNR_M32: #define __AVX512BITALG__ 1
Expand All @@ -1888,13 +1898,21 @@
// CHECK_GNR_M32: #define __AVX512VL__ 1
// CHECK_GNR_M32: #define __AVX512VNNI__ 1
// CHECK_GNR_M32: #define __AVX512VPOPCNTDQ__ 1
// CHECK_DMR_M32: #define __AVXIFMA__ 1
// CHECK_DMR_M32: #define __AVXNECONVERT__ 1
// CHECK_DMR_M32: #define __AVXVNNIINT16__ 1
// CHECK_DMR_M32: #define __AVXVNNIINT8__ 1
// CHECK_GNR_M32: #define __AVXVNNI__ 1
// CHECK_GNR_M32: #define __AVX__ 1
// CHECK_GNR_M32: #define __BMI2__ 1
// CHECK_GNR_M32: #define __BMI__ 1
// CHECK_DMR_M32: #define __CCMP__ 1
// CHECK_DMR_M32: #define __CF__ 1
// CHECK_GNR_M32: #define __CLDEMOTE__ 1
// CHECK_GNR_M32: #define __CLFLUSHOPT__ 1
// CHECK_GNR_M32: #define __CLWB__ 1
// CHECK_DMR_M32: #define __CMPCCXADD__ 1
// CHECK_DMR_M32: #define __EGPR__ 1
// CHECK_GNR_M32: #define __ENQCMD__ 1
// CHECK_GNR_M32: #define __EVEX256__ 1
// CHECK_GNR_M32: #define __EVEX512__ 1
Expand All @@ -1905,20 +1923,28 @@
// CHECK_GNR_M32: #define __LZCNT__ 1
// CHECK_GNR_M32: #define __MMX__ 1
// CHECK_GNR_M32: #define __MOVBE__ 1
// CHECK_DMR_M32: #define __MOVRS__ 1
// CHECK_DMR_M32: #define __NDD__ 1
// CHECK_DMR_M32: #define __NF__ 1
// CHECK_GNR_M32: #define __PCLMUL__ 1
// CHECK_GNR_M32: #define __PCONFIG__ 1
// CHECK_GNR_M32: #define __PKU__ 1
// CHECK_GNR_M32: #define __POPCNT__ 1
// CHECK_DMR_M32: #define __PPX__ 1
// CHECK_GNR_M32: #define __PREFETCHI__ 1
// CHECK_GNR_M32: #define __PRFCHW__ 1
// CHECK_GNR_M32: #define __PTWRITE__ 1
// CHECK_DMR_M32: #define __PUSH2POP2__ 1
// CHECK_GNR_M32: #define __RDPID__ 1
// CHECK_GNR_M32: #define __RDRND__ 1
// CHECK_GNR_M32: #define __RDSEED__ 1
// CHECK_GNR_M32: #define __SERIALIZE__ 1
// CHECK_GNR_M32: #define __SGX__ 1
// CHECK_DMR_M32: #define __SHA512__ 1
// CHECK_GNR_M32: #define __SHA__ 1
// CHECK_GNR_M32: #define __SHSTK__ 1
// CHECK_DMR_M32: #define __SM3__ 1
// CHECK_DMR_M32: #define __SM4__ 1
// CHECK_GNR_M32: #define __SSE2__ 1
// CHECK_GNR_M32: #define __SSE3__ 1
// CHECK_GNR_M32: #define __SSE4_1__ 1
Expand All @@ -1935,6 +1961,7 @@
// CHECK_GNR_M32: #define __XSAVEOPT__ 1
// CHECK_GNR_M32: #define __XSAVES__ 1
// CHECK_GNR_M32: #define __XSAVE__ 1
// CHECK_DMR_M32: #define __ZU__ 1
// CHECK_GNR_M32: #define __corei7 1
// CHECK_GNR_M32: #define __corei7__ 1
// CHECK_GNR_M32: #define __i386 1
Expand All @@ -1948,13 +1975,23 @@
// RUN: %clang -march=graniterapids-d -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=x86_64 \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64
// RUN: %clang -march=diamondrapids -m64 -E -dM %s -o - 2>&1 \
// RUN: --target=x86_64 \
// RUN: | FileCheck -match-full-lines %s -check-prefixes=CHECK_GNR_M64,CHECK_GNRD_M64,CHECK_DMR_M64
// CHECK_GNR_M64: #define __AES__ 1
// CHECK_DMR_M64: #define __AMX_AVX512__ 1
// CHECK_GNR_M64: #define __AMX_BF16__ 1
// CHECK_GNR_M64-NOT: #define __AMX_COMPLEX__ 1
// CHECK_GNRD_M64: #define __AMX_COMPLEX__ 1
// CHECK_GNR_M64: #define __AMX_FP16__ 1
// CHECK_DMR_M64: #define __AMX_FP8__ 1
// CHECK_GNR_M64: #define __AMX_INT8__ 1
// CHECK_DMR_M64: #define __AMX_MOVRS__ 1
// CHECK_DMR_M64: #define __AMX_TF32__ 1
// CHECK_GNR_M64: #define __AMX_TILE__ 1
// CHECK_DMR_M64: #define __AMX_TRANSPOSE__ 1
// CHECK_DMR_M64: #define __AVX10_2_512__ 1
// CHECK_DMR_M64: #define __AVX10_2__ 1
// CHECK_GNR_M64: #define __AVX2__ 1
// CHECK_GNR_M64: #define __AVX512BF16__ 1
// CHECK_GNR_M64: #define __AVX512BITALG__ 1
Expand All @@ -1969,13 +2006,21 @@
// CHECK_GNR_M64: #define __AVX512VL__ 1
// CHECK_GNR_M64: #define __AVX512VNNI__ 1
// CHECK_GNR_M64: #define __AVX512VPOPCNTDQ__ 1
// CHECK_DMR_M64: #define __AVXIFMA__ 1
// CHECK_DMR_M64: #define __AVXNECONVERT__ 1
// CHECK_DMR_M64: #define __AVXVNNIINT16__ 1
// CHECK_DMR_M64: #define __AVXVNNIINT8__ 1
// CHECK_GNR_M64: #define __AVXVNNI__ 1
// CHECK_GNR_M64: #define __AVX__ 1
// CHECK_GNR_M64: #define __BMI2__ 1
// CHECK_GNR_M64: #define __BMI__ 1
// CHECK_DMR_M64: #define __CCMP__ 1
// CHECK_DMR_M64: #define __CF__ 1
// CHECK_GNR_M64: #define __CLDEMOTE__ 1
// CHECK_GNR_M64: #define __CLFLUSHOPT__ 1
// CHECK_GNR_M64: #define __CLWB__ 1
// CHECK_DMR_M64: #define __CMPCCXADD__ 1
// CHECK_DMR_M64: #define __EGPR__ 1
// CHECK_GNR_M64: #define __ENQCMD__ 1
// CHECK_GNR_M64: #define __EVEX256__ 1
// CHECK_GNR_M64: #define __EVEX512__ 1
Expand All @@ -1986,20 +2031,28 @@
// CHECK_GNR_M64: #define __LZCNT__ 1
// CHECK_GNR_M64: #define __MMX__ 1
// CHECK_GNR_M64: #define __MOVBE__ 1
// CHECK_DMR_M64: #define __MOVRS__ 1
// CHECK_DMR_M64: #define __NDD__ 1
// CHECK_DMR_M64: #define __NF__ 1
// CHECK_GNR_M64: #define __PCLMUL__ 1
// CHECK_GNR_M64: #define __PCONFIG__ 1
// CHECK_GNR_M64: #define __PKU__ 1
// CHECK_GNR_M64: #define __POPCNT__ 1
// CHECK_DMR_M64: #define __PPX__ 1
// CHECK_GNR_M64: #define __PREFETCHI__ 1
// CHECK_GNR_M64: #define __PRFCHW__ 1
// CHECK_GNR_M64: #define __PTWRITE__ 1
// CHECK_DMR_M64: #define __PUSH2POP2__ 1
// CHECK_GNR_M64: #define __RDPID__ 1
// CHECK_GNR_M64: #define __RDRND__ 1
// CHECK_GNR_M64: #define __RDSEED__ 1
// CHECK_GNR_M64: #define __SERIALIZE__ 1
// CHECK_GNR_M64: #define __SGX__ 1
// CHECK_DMR_M64: #define __SHA512__ 1
// CHECK_GNR_M64: #define __SHA__ 1
// CHECK_GNR_M64: #define __SHSTK__ 1
// CHECK_DMR_M64: #define __SM3__ 1
// CHECK_DMR_M64: #define __SM4__ 1
// CHECK_GNR_M64: #define __SSE2__ 1
// CHECK_GNR_M64: #define __SSE3__ 1
// CHECK_GNR_M64: #define __SSE4_1__ 1
Expand All @@ -2016,6 +2069,7 @@
// CHECK_GNR_M64: #define __XSAVEOPT__ 1
// CHECK_GNR_M64: #define __XSAVES__ 1
// CHECK_GNR_M64: #define __XSAVE__ 1
// CHECK_DMR_M64: #define __ZU__ 1
// CHECK_GNR_M64: #define __amd64 1
// CHECK_GNR_M64: #define __amd64__ 1
// CHECK_GNR_M64: #define __corei7 1
Expand Down
14 changes: 14 additions & 0 deletions compiler-rt/lib/builtins/cpu_model/x86.c
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Expand Up @@ -103,6 +103,7 @@ enum ProcessorSubtypes {
INTEL_COREI7_ARROWLAKE_S,
INTEL_COREI7_PANTHERLAKE,
AMDFAM1AH_ZNVER5,
INTEL_COREI7_DIAMONDRAPIDS,
CPU_SUBTYPE_MAX
};

Expand Down Expand Up @@ -600,6 +601,19 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family,
break;
}
break;
case 19:
switch (Model) {
// Diamond Rapids:
case 0x01:
CPU = "diamondrapids";
*Type = INTEL_COREI7;
*Subtype = INTEL_COREI7_DIAMONDRAPIDS;
break;

default: // Unknown family 19 CPU.
break;
}
break;
default:
break; // Unknown.
}
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2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -237,6 +237,8 @@ Changes to the X86 Backend

* Supported ISA of `MSR_IMM`.

* Supported ``-mcpu=diamondrapids``

Changes to the OCaml bindings
-----------------------------

Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/X86TargetParser.def
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Expand Up @@ -107,6 +107,7 @@ X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE, "arrowlake")
X86_CPU_SUBTYPE(INTEL_COREI7_ARROWLAKE_S, "arrowlake-s")
X86_CPU_SUBTYPE(INTEL_COREI7_PANTHERLAKE, "pantherlake")
X86_CPU_SUBTYPE(AMDFAM1AH_ZNVER5, "znver5")
X86_CPU_SUBTYPE(INTEL_COREI7_DIAMONDRAPIDS, "diamondrapids")

// Alternate names supported by __builtin_cpu_is and target multiversioning.
X86_CPU_SUBTYPE_ALIAS(INTEL_COREI7_ALDERLAKE, "raptorlake")
Expand Down
1 change: 1 addition & 0 deletions llvm/include/llvm/TargetParser/X86TargetParser.h
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Expand Up @@ -121,6 +121,7 @@ enum CPUKind {
CK_GraniterapidsD,
CK_Emeraldrapids,
CK_Clearwaterforest,
CK_Diamondrapids,
CK_KNL,
CK_KNM,
CK_Lakemont,
Expand Down
29 changes: 29 additions & 0 deletions llvm/lib/Target/X86/X86.td
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Expand Up @@ -1155,6 +1155,33 @@ def ProcessorFeatures {
list<SubtargetFeature> GNRDFeatures =
!listconcat(GNRFeatures, GNRDAdditionalFeatures);

// Diamond Rapids
list<SubtargetFeature> DMRAdditionalFeatures = [FeatureAVX10_2_512,
FeatureSM4,
FeatureCMPCCXADD,
FeatureAVXIFMA,
FeatureAVXNECONVERT,
FeatureAVXVNNIINT8,
FeatureAVXVNNIINT16,
FeatureSHA512,
FeatureSM3,
FeatureEGPR,
FeatureZU,
FeatureCCMP,
FeaturePush2Pop2,
FeaturePPX,
FeatureNDD,
FeatureNF,
FeatureCF,
FeatureMOVRS,
FeatureAMXMOVRS,
FeatureAMXAVX512,
FeatureAMXFP8,
FeatureAMXTF32,
FeatureAMXTRANSPOSE];
list<SubtargetFeature> DMRFeatures =
!listconcat(GNRDFeatures, DMRAdditionalFeatures);

// Atom
list<SubtargetFeature> AtomFeatures = [FeatureX87,
FeatureCX8,
Expand Down Expand Up @@ -1856,6 +1883,8 @@ foreach P = ["graniterapids-d", "graniterapids_d"] in {
def : ProcModel<P, SapphireRapidsModel,
ProcessorFeatures.GNRDFeatures, ProcessorFeatures.GNRTuning>;
}
def : ProcModel<"diamondrapids", SapphireRapidsModel,
ProcessorFeatures.DMRFeatures, ProcessorFeatures.GNRTuning>;

// AMD CPUs.

Expand Down
13 changes: 13 additions & 0 deletions llvm/lib/TargetParser/Host.cpp
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Expand Up @@ -1010,6 +1010,19 @@ static StringRef getIntelProcessorTypeAndSubtype(unsigned Family,
CPU = "pentium4";
break;
}
case 19:
switch (Model) {
// Diamond Rapids:
case 0x01:
CPU = "diamondrapids";
*Type = X86::INTEL_COREI7;
*Subtype = X86::INTEL_COREI7_DIAMONDRAPIDS;
break;

default: // Unknown family 19 CPU.
break;
}
break;
default:
break; // Unknown.
}
Expand Down
10 changes: 10 additions & 0 deletions llvm/lib/TargetParser/X86TargetParser.cpp
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Expand Up @@ -138,6 +138,14 @@ constexpr FeatureBitset FeaturesSapphireRapids =
FeatureWAITPKG;
constexpr FeatureBitset FeaturesGraniteRapids =
FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI;
constexpr FeatureBitset FeaturesDiamondRapids =
FeaturesGraniteRapids | FeatureAMX_COMPLEX | FeatureAVX10_2_512 |
FeatureCMPCCXADD | FeatureAVXIFMA | FeatureAVXNECONVERT |
FeatureAVXVNNIINT8 | FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 |
FeatureSM4 | FeatureEGPR | FeatureZU | FeatureCCMP | FeaturePush2Pop2 |
FeaturePPX | FeatureNDD | FeatureNF | FeatureCF | FeatureMOVRS |
FeatureAMX_MOVRS | FeatureAMX_AVX512 | FeatureAMX_FP8 | FeatureAMX_TF32 |
FeatureAMX_TRANSPOSE;

// Intel Atom processors.
// Bonnell has feature parity with Core2 and adds MOVBE.
Expand Down Expand Up @@ -381,6 +389,8 @@ constexpr ProcInfo Processors[] = {
{ {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false },
// Clearwaterforest microarchitecture based processors.
{ {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false },
// Diamond Rapids microarchitecture based processors.
{ {"diamondrapids"}, CK_Diamondrapids, FEATURE_AVX10_2_512, FeaturesDiamondRapids, 'z', false },
// Knights Landing processor.
{ {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false },
{ {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true },
Expand Down
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