[LoongArch] Adds support for vectors in OptWInstrs

[heiher]

No description provided.

[llvmbot]

@llvm/pr-subscribers-backend-loongarch

Author: hev (heiher)

Changes

---

Full diff: https://github.com/llvm/llvm-project/pull/118935.diff

2 Files Affected:

• (modified) llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp (+29-2)
• (modified) llvm/test/CodeGen/LoongArch/sextw-removal.ll (-1)

diff --git a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
index ab90409fdf47d0..73e8be0f9522af 100644
--- a/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
@@ -126,7 +126,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
 
       switch (UserMI->getOpcode()) {
       default:
-        // TODO: Add vector
         return false;
 
       case LoongArch::ADD_W:
@@ -167,18 +166,45 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
       case LoongArch::MOVGR2FCSR:
       case LoongArch::MOVGR2FRH_W:
       case LoongArch::MOVGR2FR_W_64:
+      case LoongArch::VINSGR2VR_W:
+      case LoongArch::XVINSGR2VR_W:
+      case LoongArch::VREPLGR2VR_W:
+      case LoongArch::XVREPLGR2VR_W:
         if (Bits >= 32)
           break;
         return false;
       case LoongArch::MOVGR2CF:
+      case LoongArch::VREPLVE_D:
+      case LoongArch::XVREPLVE_D:
         if (Bits >= 1)
           break;
         return false;
+      case LoongArch::VREPLVE_W:
+      case LoongArch::XVREPLVE_W:
+        if (Bits >= 2)
+          break;
+        return false;
+      case LoongArch::VREPLVE_H:
+      case LoongArch::XVREPLVE_H:
+        if (Bits >= 3)
+          break;
+        return false;
+      case LoongArch::VREPLVE_B:
+      case LoongArch::XVREPLVE_B:
+        if (Bits >= 4)
+          break;
+        return false;
       case LoongArch::EXT_W_B:
+      case LoongArch::VINSGR2VR_B:
+      case LoongArch::VREPLGR2VR_B:
+      case LoongArch::XVREPLGR2VR_B:
         if (Bits >= 8)
           break;
         return false;
       case LoongArch::EXT_W_H:
+      case LoongArch::VINSGR2VR_H:
+      case LoongArch::VREPLGR2VR_H:
+      case LoongArch::XVREPLGR2VR_H:
         if (Bits >= 16)
           break;
         return false;
@@ -431,7 +457,8 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
   case LoongArch::MOVCF2GR:
   case LoongArch::MOVFRH2GR_S:
   case LoongArch::MOVFR2GR_S_64:
-    // TODO: Add vector
+  case LoongArch::VPICKVE2GR_W:
+  case LoongArch::XVPICKVE2GR_W:
     return true;
   // Special cases that require checking operands.
   // shifting right sufficiently makes the value 32-bit sign-extended
diff --git a/llvm/test/CodeGen/LoongArch/sextw-removal.ll b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
index 0aeafadb9325b8..c625f2db4d2e89 100644
--- a/llvm/test/CodeGen/LoongArch/sextw-removal.ll
+++ b/llvm/test/CodeGen/LoongArch/sextw-removal.ll
@@ -1322,7 +1322,6 @@ define signext i32 @test20(<4 x i32> %v) {
 ; CHECK-LABEL: test20:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vpickve2gr.w $a0, $vr0, 3
-; CHECK-NEXT:    addi.w $a0, $a0, 0
 ; CHECK-NEXT:    ret
 ;
 ; NORMV-LABEL: test20:

[SixWeining]

Is it possible to add some tests for these instructions?

[heiher]

I've added test cases for the vreplgr2vr.w instruction. For vector instructions, effective optimizations often arise in cases involving complex multi-level data flow relationships. I plan to add more test cases in the future if I identify opportunities for further simplification.