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[LoongArch] Adds support for vectors in OptWInstrs #118935

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Merged
merged 3 commits into from
Dec 16, 2024
Merged

[LoongArch] Adds support for vectors in OptWInstrs #118935

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fe6638a
[LoongArch] Adds support for vectors in OptWInstrs
heiher Dec 5, 2024
4eb59fe
Merge remote-tracking branch 'origin/main' into sextw-rmv-vec
heiher Dec 13, 2024
3ad015a
Update test case
heiher Dec 13, 2024
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31 changes: 29 additions & 2 deletions llvm/lib/Target/LoongArch/LoongArchOptWInstrs.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -126,7 +126,6 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,

switch (UserMI->getOpcode()) {
default:
// TODO: Add vector
return false;

case LoongArch::ADD_W:
Expand Down Expand Up @@ -162,6 +161,10 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
case LoongArch::MOVGR2FCSR:
case LoongArch::MOVGR2FRH_W:
case LoongArch::MOVGR2FR_W_64:
case LoongArch::VINSGR2VR_W:
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Is it possible to add some tests for these instructions?

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I've added test cases for the vreplgr2vr.w instruction. For vector instructions, effective optimizations often arise in cases involving complex multi-level data flow relationships. I plan to add more test cases in the future if I identify opportunities for further simplification.

case LoongArch::XVINSGR2VR_W:
case LoongArch::VREPLGR2VR_W:
case LoongArch::XVREPLGR2VR_W:
if (Bits >= 32)
break;
return false;
Expand All @@ -175,14 +178,37 @@ static bool hasAllNBitUsers(const MachineInstr &OrigMI,
break;
return false;
case LoongArch::MOVGR2CF:
case LoongArch::VREPLVE_D:
case LoongArch::XVREPLVE_D:
if (Bits >= 1)
break;
return false;
case LoongArch::VREPLVE_W:
case LoongArch::XVREPLVE_W:
if (Bits >= 2)
break;
return false;
case LoongArch::VREPLVE_H:
case LoongArch::XVREPLVE_H:
if (Bits >= 3)
break;
return false;
case LoongArch::VREPLVE_B:
case LoongArch::XVREPLVE_B:
if (Bits >= 4)
break;
return false;
case LoongArch::EXT_W_B:
case LoongArch::VINSGR2VR_B:
case LoongArch::VREPLGR2VR_B:
case LoongArch::XVREPLGR2VR_B:
if (Bits >= 8)
break;
return false;
case LoongArch::EXT_W_H:
case LoongArch::VINSGR2VR_H:
case LoongArch::VREPLGR2VR_H:
case LoongArch::XVREPLGR2VR_H:
if (Bits >= 16)
break;
return false;
Expand Down Expand Up @@ -435,7 +461,8 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
case LoongArch::MOVCF2GR:
case LoongArch::MOVFRH2GR_S:
case LoongArch::MOVFR2GR_S_64:
// TODO: Add vector
case LoongArch::VPICKVE2GR_W:
case LoongArch::XVPICKVE2GR_W:
return true;
// Special cases that require checking operands.
// shifting right sufficiently makes the value 32-bit sign-extended
Expand Down
8 changes: 3 additions & 5 deletions llvm/test/CodeGen/LoongArch/sextw-removal.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1322,7 +1322,6 @@ define signext i32 @test20(<4 x i32> %v) {
; CHECK-LABEL: test20:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
; CHECK-NEXT: addi.w $a0, $a0, 0
; CHECK-NEXT: ret
;
; NORMV-LABEL: test20:
Expand Down Expand Up @@ -1358,7 +1357,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
; CHECK-NEXT: .cfi_offset 27, -56
; CHECK-NEXT: .cfi_offset 28, -64
; CHECK-NEXT: .cfi_offset 29, -72
; CHECK-NEXT: ld.d $s6, $sp, 80
; CHECK-NEXT: ld.w $s6, $sp, 80
; CHECK-NEXT: move $s2, $a7
; CHECK-NEXT: move $s4, $a5
; CHECK-NEXT: move $s0, $a4
Expand All @@ -1379,8 +1378,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
; CHECK-NEXT: .LBB24_3: # %for.cond32.preheader.preheader
; CHECK-NEXT: ld.d $a0, $sp, 96
; CHECK-NEXT: ld.d $a1, $sp, 88
; CHECK-NEXT: addi.w $a2, $s6, 0
; CHECK-NEXT: sltui $a2, $a2, 1
; CHECK-NEXT: sltui $a2, $s6, 1
; CHECK-NEXT: masknez $a0, $a0, $a2
; CHECK-NEXT: vreplgr2vr.w $vr0, $s6
; CHECK-NEXT: andi $a1, $a1, 1
Expand Down Expand Up @@ -1452,7 +1450,7 @@ define fastcc ptr @test21(ptr %B, ptr %Op0, ptr %Op1, ptr %P, ptr %M, i1 zeroext
; NORMV-NEXT: beqz $s4, .LBB24_2
; NORMV-NEXT: # %bb.1: # %if.then26
; NORMV-NEXT: addi.d $a0, $s6, 1
; NORMV-NEXT: addi.w $s6, $a0, 0
; NORMV-NEXT: addi.d $s6, $a0, 0
; NORMV-NEXT: beqz $s4, .LBB24_3
; NORMV-NEXT: b .LBB24_6
; NORMV-NEXT: .LBB24_2:
Expand Down
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