[NFC] [RISCV] Refactor class RISCVExtension #120040
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@llvm/pr-subscribers-clang @llvm/pr-subscribers-backend-risc-v Author: Shao-Ce SUN (sunshaoce) ChangesI think typo can be avoided by reducing the number of times we re-enter the extension name. Patch is 95.42 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/120040.diff 2 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e770c39f42abfa..46cacdc1005a08 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -22,11 +22,17 @@
// uses the record name by replacing Feature with Has.
// value - Value to assign to the field in RISCVSubtarget when this
// extension is enabled. Usually "true", but can be changed.
-class RISCVExtension<string name, int major, int minor, string desc,
+class RISCVExtension<int major, int minor, string desc,
list<SubtargetFeature> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
- string value = "true">
- : SubtargetFeature<name, fieldname, value, desc, implies> {
+ string value = "true", string prefix = "">
+ : SubtargetFeature<
+ prefix # !tolower(!subst("FeatureVendor", "",
+ !subst("FeatureStdExt", "", NAME))),
+ fieldname, value,
+ "'" # !subst("FeatureVendor", "", !subst("FeatureStdExt", "", NAME))
+ # "' (" # desc # ")",
+ implies> {
// MajorVersion - The major version for this extension.
int MajorVersion = major;
@@ -37,7 +43,7 @@ class RISCVExtension<string name, int major, int minor, string desc,
bit Experimental = false;
}
-// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value
+// The groupID/bitmask of RISCVExtension is used to retrieve a specific bit value
// from __riscv_feature_bits based on the groupID and bitmask.
// groupID - groupID of extension
// bitPos - bit position of extension bitmask
@@ -48,125 +54,108 @@ class RISCVExtensionBitmask<bits<3> groupID, int bitPos> {
// Version of RISCVExtension to be used for Experimental extensions. This
// sets the Experimental flag and prepends experimental- to the -mattr name.
-class RISCVExperimentalExtension<string name, int major, int minor, string desc,
+class RISCVExperimentalExtension<int major, int minor, string desc,
list<RISCVExtension> implies = [],
string fieldname = !subst("Feature", "Has", NAME),
string value = "true">
- : RISCVExtension<"experimental-"#name, major, minor, desc, implies,
- fieldname, value> {
+ : RISCVExtension<major, minor, desc, implies, fieldname, value,
+ "experimental-"> {
let Experimental = true;
}
// Integer Extensions
def FeatureStdExtI
- : RISCVExtension<"i", 2, 1,
- "'I' (Base Integer Instruction Set)">,
+ : RISCVExtension<2, 1, "Base Integer Instruction Set">,
RISCVExtensionBitmask<0, 8>;
def FeatureStdExtE
- : RISCVExtension<"e", 2, 0,
- "Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
+ : RISCVExtension<2, 0, "Embedded Instruction Set with 16 GPRs">;
def FeatureStdExtZic64b
- : RISCVExtension<"zic64b", 1, 0,
- "'Zic64b' (Cache Block Size Is 64 Bytes)">;
+ : RISCVExtension<1, 0, "Cache Block Size Is 64 Bytes">;
def FeatureStdExtZicbom
- : RISCVExtension<"zicbom", 1, 0,
- "'Zicbom' (Cache-Block Management Instructions)">;
+ : RISCVExtension<1, 0, "Cache-Block Management Instructions">;
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
AssemblerPredicate<(all_of FeatureStdExtZicbom),
"'Zicbom' (Cache-Block Management Instructions)">;
def FeatureStdExtZicbop
- : RISCVExtension<"zicbop", 1, 0,
- "'Zicbop' (Cache-Block Prefetch Instructions)">;
+ : RISCVExtension<1, 0, "Cache-Block Prefetch Instructions">;
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
AssemblerPredicate<(all_of FeatureStdExtZicbop),
"'Zicbop' (Cache-Block Prefetch Instructions)">;
def FeatureStdExtZicboz
- : RISCVExtension<"zicboz", 1, 0,
- "'Zicboz' (Cache-Block Zero Instructions)">,
+ : RISCVExtension<1, 0, "Cache-Block Zero Instructions">,
RISCVExtensionBitmask<0, 37>;
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
AssemblerPredicate<(all_of FeatureStdExtZicboz),
"'Zicboz' (Cache-Block Zero Instructions)">;
def FeatureStdExtZiccamoa
- : RISCVExtension<"ziccamoa", 1, 0,
- "'Ziccamoa' (Main Memory Supports All Atomics in A)">;
+ : RISCVExtension<1, 0, "Main Memory Supports All Atomics in A">;
def FeatureStdExtZiccif
- : RISCVExtension<"ziccif", 1, 0,
- "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)">;
+ : RISCVExtension<1, 0,
+ "Main Memory Supports Instruction Fetch with Atomicity Requirement">;
def FeatureStdExtZicclsm
- : RISCVExtension<"zicclsm", 1, 0,
- "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)">;
+ : RISCVExtension<1, 0, "Main Memory Supports Misaligned Loads/Stores">;
def FeatureStdExtZiccrse
- : RISCVExtension<"ziccrse", 1, 0,
- "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)">;
+ : RISCVExtension<1, 0,
+ "Main Memory Supports Forward Progress on LR/SC Sequences">;
def FeatureStdExtZicsr
- : RISCVExtension<"zicsr", 2, 0,
- "'zicsr' (CSRs)">;
+ : RISCVExtension<2, 0, "CSRs">;
def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
def FeatureStdExtZicntr
- : RISCVExtension<"zicntr", 2, 0,
- "'Zicntr' (Base Counters and Timers)",
- [FeatureStdExtZicsr]>;
+ : RISCVExtension<2, 0, "Base Counters and Timers",
+ [FeatureStdExtZicsr]>;
def FeatureStdExtZicond
- : RISCVExtension<"zicond", 1, 0,
- "'Zicond' (Integer Conditional Operations)">,
+ : RISCVExtension<1, 0, "Integer Conditional Operations">,
RISCVExtensionBitmask<0, 38>;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
- "'Zicond' (Integer Conditional Operations)">;
+ "(Integer Conditional Operations)">;
def FeatureStdExtZifencei
- : RISCVExtension<"zifencei", 2, 0,
- "'Zifencei' (fence.i)">;
+ : RISCVExtension<2, 0, "fence.i">;
def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
AssemblerPredicate<(all_of FeatureStdExtZifencei),
"'Zifencei' (fence.i)">;
def FeatureStdExtZihintpause
- : RISCVExtension<"zihintpause", 2, 0,
- "'Zihintpause' (Pause Hint)">,
+ : RISCVExtension<2, 0, "Pause Hint">,
RISCVExtensionBitmask<0, 40>;
def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
AssemblerPredicate<(all_of FeatureStdExtZihintpause),
"'Zihintpause' (Pause Hint)">;
def FeatureStdExtZihintntl
- : RISCVExtension<"zihintntl", 1, 0,
- "'Zihintntl' (Non-Temporal Locality Hints)">,
+ : RISCVExtension<1, 0, "Non-Temporal Locality Hints">,
RISCVExtensionBitmask<0, 39>;
def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
AssemblerPredicate<(all_of FeatureStdExtZihintntl),
"'Zihintntl' (Non-Temporal Locality Hints)">;
def FeatureStdExtZihpm
- : RISCVExtension<"zihpm", 2, 0,
- "'Zihpm' (Hardware Performance Counters)",
+ : RISCVExtension<2, 0, "Hardware Performance Counters",
[FeatureStdExtZicsr]>;
-def FeatureStdExtZimop : RISCVExtension<"zimop", 1, 0,
- "'Zimop' (May-Be-Operations)">;
+def FeatureStdExtZimop : RISCVExtension<1, 0, "May-Be-Operations">;
def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">,
AssemblerPredicate<(all_of FeatureStdExtZimop),
"'Zimop' (May-Be-Operations)">;
def FeatureStdExtZicfilp
- : RISCVExperimentalExtension<"zicfilp", 1, 0,
- "'Zicfilp' (Landing pad)",
+ : RISCVExperimentalExtension<1, 0, "Landing pad",
[FeatureStdExtZicsr]>;
def HasStdExtZicfilp : Predicate<"Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of FeatureStdExtZicfilp),
@@ -175,8 +164,7 @@ def NoStdExtZicfilp : Predicate<"!Subtarget->hasStdExtZicfilp()">,
AssemblerPredicate<(all_of (not FeatureStdExtZicfilp))>;
def FeatureStdExtZicfiss
- : RISCVExperimentalExtension<"zicfiss", 1, 0,
- "'Zicfiss' (Shadow stack)",
+ : RISCVExperimentalExtension<1, 0, "Shadow stack",
[FeatureStdExtZicsr, FeatureStdExtZimop]>;
def HasStdExtZicfiss : Predicate<"Subtarget->hasStdExtZicfiss()">,
AssemblerPredicate<(all_of FeatureStdExtZicfiss),
@@ -186,15 +174,13 @@ def NoHasStdExtZicfiss : Predicate<"!Subtarget->hasStdExtZicfiss()">;
// Multiply Extensions
def FeatureStdExtZmmul
- : RISCVExtension<"zmmul", 1, 0,
- "'Zmmul' (Integer Multiplication)">;
+ : RISCVExtension<1, 0, "Integer Multiplication">;
def HasStdExtZmmul : Predicate<"Subtarget->hasStdExtZmmul()">,
AssemblerPredicate<(all_of FeatureStdExtZmmul),
"'Zmmul' (Integer Multiplication)">;
def FeatureStdExtM
- : RISCVExtension<"m", 2, 0,
- "'M' (Integer Multiplication and Division)",
+ : RISCVExtension<2, 0, "Integer Multiplication and Division",
[FeatureStdExtZmmul]>,
RISCVExtensionBitmask<0, 12>;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
@@ -204,24 +190,21 @@ def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
// Atomic Extensions
def FeatureStdExtZaamo
- : RISCVExtension<"zaamo", 1, 0,
- "'Zaamo' (Atomic Memory Operations)">;
+ : RISCVExtension<1, 0, "Atomic Memory Operations">;
def HasStdExtZaamo
: Predicate<"Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtZaamo),
"'Zaamo' (Atomic Memory Operations)">;
def FeatureStdExtZalrsc
- : RISCVExtension<"zalrsc", 1, 0,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+ : RISCVExtension<1, 0, "Load-Reserved/Store-Conditional">;
def HasStdExtZalrsc
: Predicate<"Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtZalrsc),
"'Zalrsc' (Load-Reserved/Store-Conditional)">;
def FeatureStdExtA
- : RISCVExtension<"a", 2, 1,
- "'A' (Atomic Instructions)",
+ : RISCVExtension<2, 1, "Atomic Instructions",
[FeatureStdExtZaamo, FeatureStdExtZalrsc]>,
RISCVExtensionBitmask<0, 0>;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
@@ -229,31 +212,28 @@ def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
"'A' (Atomic Instructions)">;
def FeatureStdExtZtso
- : RISCVExtension<"ztso", 1, 0,
- "'Ztso' (Memory Model - Total Store Order)">,
+ : RISCVExtension<1, 0, "Memory Model - Total Store Order">,
RISCVExtensionBitmask<0, 47>;
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
-def FeatureStdExtZa64rs : RISCVExtension<"za64rs", 1, 0,
- "'Za64rs' (Reservation Set Size of at Most 64 Bytes)">;
+def FeatureStdExtZa64rs
+ : RISCVExtension<1, 0, "Reservation Set Size of at Most 64 Bytes">;
-def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
- "'Za128rs' (Reservation Set Size of at Most 128 Bytes)">;
+def FeatureStdExtZa128rs
+ : RISCVExtension<1, 0, "Reservation Set Size of at Most 128 Bytes">;
def FeatureStdExtZabha
- : RISCVExtension<"zabha", 1, 0,
- "'Zabha' (Byte and Halfword Atomic Memory Operations)",
+ : RISCVExtension<1, 0, "Byte and Halfword Atomic Memory Operations",
[FeatureStdExtZaamo]>;
def HasStdExtZabha : Predicate<"Subtarget->hasStdExtZabha()">,
AssemblerPredicate<(all_of FeatureStdExtZabha),
"'Zabha' (Byte and Halfword Atomic Memory Operations)">;
def FeatureStdExtZacas
- : RISCVExtension<"zacas", 1, 0,
- "'Zacas' (Atomic Compare-And-Swap Instructions)",
+ : RISCVExtension<1, 0, "Atomic Compare-And-Swap Instructions",
[FeatureStdExtZaamo]>,
RISCVExtensionBitmask<0, 26>;
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
@@ -262,18 +242,15 @@ def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
def NoStdExtZacas : Predicate<"!Subtarget->hasStdExtZacas()">;
def FeatureStdExtZalasr
- : RISCVExperimentalExtension<"zalasr", 0, 1,
- "'Zalasr' (Load-Acquire and Store-Release Instructions)">;
+ : RISCVExperimentalExtension<0, 1, "Load-Acquire and Store-Release Instructions">;
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
AssemblerPredicate<(all_of FeatureStdExtZalasr),
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
def FeatureStdExtZama16b
- : RISCVExtension<"zama16b", 1, 0,
- "'Zama16b' (Atomic 16-byte misaligned loads, stores and AMOs)">;
+ : RISCVExtension<1, 0, "Atomic 16-byte misaligned loads, stores and AMOs">;
-def FeatureStdExtZawrs : RISCVExtension<"zawrs", 1, 0,
- "'Zawrs' (Wait on Reservation Set)">;
+def FeatureStdExtZawrs : RISCVExtension<1, 0, "Wait on Reservation Set">;
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
AssemblerPredicate<(all_of FeatureStdExtZawrs),
"'Zawrs' (Wait on Reservation Set)">;
@@ -281,8 +258,7 @@ def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
// Floating Point Extensions
def FeatureStdExtF
- : RISCVExtension<"f", 2, 2,
- "'F' (Single-Precision Floating-Point)",
+ : RISCVExtension<2, 2, "Single-Precision Floating-Point",
[FeatureStdExtZicsr]>,
RISCVExtensionBitmask<0, 5>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
@@ -290,8 +266,7 @@ def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
"'F' (Single-Precision Floating-Point)">;
def FeatureStdExtD
- : RISCVExtension<"d", 2, 2,
- "'D' (Double-Precision Floating-Point)",
+ : RISCVExtension<2, 2, "Double-Precision Floating-Point",
[FeatureStdExtF]>,
RISCVExtensionBitmask<0, 3>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
@@ -299,8 +274,7 @@ def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
"'D' (Double-Precision Floating-Point)">;
def FeatureStdExtZfhmin
- : RISCVExtension<"zfhmin", 1, 0,
- "'Zfhmin' (Half-Precision Floating-Point Minimal)",
+ : RISCVExtension<1, 0, "Half-Precision Floating-Point Minimal",
[FeatureStdExtF]>,
RISCVExtensionBitmask<0, 36>;
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
@@ -309,8 +283,7 @@ def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
def FeatureStdExtZfh
- : RISCVExtension<"zfh", 1, 0,
- "'Zfh' (Half-Precision Floating-Point)",
+ : RISCVExtension<1, 0, "Half-Precision Floating-Point",
[FeatureStdExtZfhmin]>,
RISCVExtensionBitmask<0, 35>;
def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
@@ -319,8 +292,7 @@ def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
def FeatureStdExtZfbfmin
- : RISCVExtension<"zfbfmin", 1, 0, "'Zfbfmin' (Scalar BF16 Converts)",
- [FeatureStdExtF]>;
+ : RISCVExtension<1, 0, "Scalar BF16 Converts", [FeatureStdExtF]>;
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
"'Zfbfmin' (Scalar BF16 Converts)">;
@@ -334,18 +306,14 @@ def HasHalfFPLoadStoreMove
"'Zfbfmin' (Scalar BF16 Converts)">;
def FeatureStdExtZfa
- : RISCVExtension<"zfa", 1, 0,
- "'Zfa' (Additional Floating-Point)",
- [FeatureStdExtF]>,
+ : RISCVExtension<1, 0, "Additional Floating-Point", [FeatureStdExtF]>,
RISCVExtensionBitmask<0, 34>;
def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
AssemblerPredicate<(all_of FeatureStdExtZfa),
"'Zfa' (Additional Floating-Point)">;
def FeatureStdExtZfinx
- : RISCVExtension<"zfinx", 1, 0,
- "'Zfinx' (Float in Integer)",
- [FeatureStdExtZicsr]>;
+ : RISCVExtension<1, 0, "Float in Integer", [FeatureStdExtZicsr]>;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
@@ -356,16 +324,13 @@ def HasStdExtFOrZfinx : Predicate<"Subtarget->hasStdExtFOrZfinx()">,
"'Zfinx' (Float in Integer)">;
def FeatureStdExtZdinx
- : RISCVExtension<"zdinx", 1, 0,
- "'Zdinx' (Double in Integer)",
- [FeatureStdExtZfinx]>;
+ : RISCVExtension<1, 0, "Double in Integer", [FeatureStdExtZfinx]>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
def FeatureStdExtZhinxmin
- : RISCVExtension<"zhinxmin", 1, 0,
- "'Zhinxmin' (Half Float in Integer Minimal)",
+ : RISCVExtension<1, 0, "Half Float in Integer Minimal",
[FeatureStdExtZfinx]>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
@@ -373,9 +338,7 @@ def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
"'Zhinxmin' (Half Float in Integer Minimal)">;
def FeatureStdExtZhinx
- : RISCVExtension<"zhinx", 1, 0,
- "'Zhinx' (Half Float in Integer)",
- [FeatureStdExtZhinxmin]>;
+ : RISCVExtension<1, 0, "Half Float in Integer", [FeatureStdExtZhinxmin]>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
@@ -384,8 +347,7 @@ def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
// Compressed Extensions
def FeatureStdExtC
- : RISCVExtension<"c", 2, 0,
- "'C' (Compressed Instructions)">,
+ : RISCVExtension<2, 0, "Compressed Instructions">,
RISCVExtensionBitmask<0, 2>;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtC),
@@ -399,9 +361,9 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
"RVC Hint Instructions">;
...
[truncated]
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/10397 Here is the relevant piece of the build log for the reference |
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I think typo can be avoided by reducing the number of times we re-enter the extension name.