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[NFC] [RISCV] Refactor class RISCVExtension #120040

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Merged
merged 8 commits into from
Dec 16, 2024
Merged

[NFC] [RISCV] Refactor class RISCVExtension #120040

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77730fa
[RISCV] Add a test of riscv features
sunshaoce Dec 16, 2024
4f201f8
[NFC] [RISCV] Refactor class RISCVExtension
sunshaoce Dec 16, 2024
3d0c916
fixup! Fix failed clang tests
sunshaoce Dec 16, 2024
0be203c
fixup! use IsExperimental
sunshaoce Dec 16, 2024
a248fa9
fixup! override Name & Desc
sunshaoce Dec 16, 2024
d4336e6
fixup! Add note for extension name
sunshaoce Dec 16, 2024
f53c427
fixup! Use ExtName
sunshaoce Dec 16, 2024
becf858
fixup! use extName
sunshaoce Dec 16, 2024
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10 changes: 5 additions & 5 deletions clang/test/Driver/print-enabled-extensions/riscv-rocket-rv64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@
// Simple litmus test to check the frontend handling of this option is
// enabled.

// CHECK: Extensions enabled for the given RISC-V target
// CHECK: Extensions enabled for the given RISC-V target
// CHECK-EMPTY:
// CHECK-NEXT: Name Version Description
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
// CHECK-NEXT: zicsr 2.0 'zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: Name Version Description
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-EMPTY:
40 changes: 20 additions & 20 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
// CHECK-EMPTY:
// CHECK-NEXT: Name Version Description
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
// CHECK-NEXT: e 2.0 Implements RV{32,64}E (provides 16 rather than 32 GPRs)
// CHECK-NEXT: e 2.0 'E' (Embedded Instruction Set with 16 GPRs)
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
Expand All @@ -24,7 +24,7 @@
// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)
// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers)
// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations)
// CHECK-NEXT: zicsr 2.0 'zicsr' (CSRs)
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints)
// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint)
Expand Down Expand Up @@ -78,7 +78,7 @@
// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)
// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)
// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)
// CHECK-NEXT: zvfbfmin 1.0 'Zvbfmin' (Vector BF16 Converts)
// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts)
// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add)
// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point)
// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)
Expand All @@ -87,7 +87,7 @@
// CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')
// CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')
// CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round))
// CHECK-NEXT: zvkng 1.0 'zvkng' (shorthand for 'Zvkn' and 'Zvkg')
// CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg')
// CHECK-NEXT: zvknha 1.0 'Zvknha' (Vector SHA-2 (SHA-256 only))
// CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))
// CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')
Expand All @@ -96,25 +96,25 @@
// CHECK-NEXT: zvksg 1.0 'Zvksg' (shorthand for 'Zvks' and 'Zvkg')
// CHECK-NEXT: zvksh 1.0 'Zvksh' (SM3 Hash Function Instructions)
// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency)
// CHECK-NEXT: zvl1024b 1.0 'Zvl' (Minimum Vector Length) 1024
// CHECK-NEXT: zvl128b 1.0 'Zvl' (Minimum Vector Length) 128
// CHECK-NEXT: zvl16384b 1.0 'Zvl' (Minimum Vector Length) 16384
// CHECK-NEXT: zvl2048b 1.0 'Zvl' (Minimum Vector Length) 2048
// CHECK-NEXT: zvl256b 1.0 'Zvl' (Minimum Vector Length) 256
// CHECK-NEXT: zvl32768b 1.0 'Zvl' (Minimum Vector Length) 32768
// CHECK-NEXT: zvl32b 1.0 'Zvl' (Minimum Vector Length) 32
// CHECK-NEXT: zvl4096b 1.0 'Zvl' (Minimum Vector Length) 4096
// CHECK-NEXT: zvl512b 1.0 'Zvl' (Minimum Vector Length) 512
// CHECK-NEXT: zvl64b 1.0 'Zvl' (Minimum Vector Length) 64
// CHECK-NEXT: zvl65536b 1.0 'Zvl' (Minimum Vector Length) 65536
// CHECK-NEXT: zvl8192b 1.0 'Zvl' (Minimum Vector Length) 8192
// CHECK-NEXT: zvl1024b 1.0 'Zvl1024b' (Minimum Vector Length 1024)
// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128)
// CHECK-NEXT: zvl16384b 1.0 'Zvl16384b' (Minimum Vector Length 16384)
// CHECK-NEXT: zvl2048b 1.0 'Zvl2048b' (Minimum Vector Length 2048)
// CHECK-NEXT: zvl256b 1.0 'Zvl256b' (Minimum Vector Length 256)
// CHECK-NEXT: zvl32768b 1.0 'Zvl32768b' (Minimum Vector Length 32768)
// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32)
// CHECK-NEXT: zvl4096b 1.0 'Zvl4096b' (Minimum Vector Length 4096)
// CHECK-NEXT: zvl512b 1.0 'Zvl512b' (Minimum Vector Length 512)
// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64)
// CHECK-NEXT: zvl65536b 1.0 'Zvl65536b' (Minimum Vector Length 65536)
// CHECK-NEXT: zvl8192b 1.0 'Zvl8192b' (Minimum Vector Length 8192)
// CHECK-NEXT: zhinx 1.0 'Zhinx' (Half Float in Integer)
// CHECK-NEXT: zhinxmin 1.0 'Zhinxmin' (Half Float in Integer Minimal)
// CHECK-NEXT: sha 1.0 'Sha' (Augmented Hypervisor)
// CHECK-NEXT: shcounterenw 1.0 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: shgatpa 1.0 'Sgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
// CHECK-NEXT: shgatpa 1.0 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare)
// CHECK-NEXT: shtvala 1.0 'Shtvala' (htval provides all needed values)
// CHECK-NEXT: shvsatpa 1.0 'Svsatpa' (vsatp supports all modes supported by satp)
// CHECK-NEXT: shvsatpa 1.0 'Shvsatpa' (vsatp supports all modes supported by satp)
// CHECK-NEXT: shvstvala 1.0 'Shvstvala' (vstval provides all needed values)
// CHECK-NEXT: shvstvecd 1.0 'Shvstvecd' (vstvec supports Direct mode)
// CHECK-NEXT: smaia 1.0 'Smaia' (Advanced Interrupt Architecture Machine Level)
Expand Down Expand Up @@ -145,11 +145,11 @@
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
// CHECK-NEXT: svadu 1.0 'Svadu' (Hardware A/D updates)
// CHECK-NEXT: svbare 1.0 'Svbare' $(satp mode Bare supported)
// CHECK-NEXT: svbare 1.0 'Svbare' (satp mode Bare supported)
// CHECK-NEXT: svinval 1.0 'Svinval' (Fine-Grained Address-Translation Cache Invalidation)
// CHECK-NEXT: svnapot 1.0 'Svnapot' (NAPOT Translation Contiguity)
// CHECK-NEXT: svpbmt 1.0 'Svpbmt' (Page-Based Memory Types)
// CHECK-NEXT: svvptc 1.0 'svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: svvptc 1.0 'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)
// CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations)
// CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching)
// CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation)
Expand Down
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