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[RISCV][VLOPT] Add vfirst and vcpop to getOperandInfo #122295

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Merged
merged 2 commits into from
Jan 9, 2025
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[RISCV][VLOPT] Add vfirst and vcpop to getOperandInfo #122295

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[RISCV][VLOPT] Add vfirst and vcpop to getOperandInfo
michaelmaitland Jan 9, 2025
641d124
fixup! fix typo
michaelmaitland Jan 9, 2025
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -488,6 +488,10 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
case RISCV::VFCVT_F_X_V:
// Vector Floating-Point Merge Instruction
case RISCV::VFMERGE_VFM:
// Vector count population in mask vcpop.m
// vfirst find-first-set mask bit
case RISCV::VCPOP_M:
case RISCV::VFIRST_M:
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Shouldn't the source operand for these both be a mask operand and thus 0? Or is it the case that the MILog2SEW is guaranteed to be zero in this case?

After thinking about it for a bit, I think that is the case. Please confirm, but consider this a non-blocking comment as long as that is in fact true.

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Or is it the case that the MILog2SEW is guaranteed to be zero in this case?

That is correct. And since the source operand may not be vmv0, we need to handle it here.

return MILog2SEW;

// Vector Widening Integer Add/Subtract
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60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
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Expand Up @@ -1438,3 +1438,63 @@ body: |
%x:vr = nofpexcept PseudoVFCVT_X_F_V_M1 $noreg, $noreg, 0, -1, 5 /* e32 */, 0
%y:vr = PseudoVFREDMAX_VS_MF2_E32 $noreg, %x, %x, 1, 5 /* e32 */, 0
...
---
name: vfirst_v
body: |
bb.0:
; CHECK-LABEL: name: vfirst_v
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 /* e8 */
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
%y:gpr = PseudoVFIRST_M_B8 %x, 1, 0
...
---
name: vfirst_v_incompatible_eew
body: |
bb.0:
; CHECK-LABEL: name: vfirst_v_incompatible_eew
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B8 %x, 1, 0 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:gpr = PseudoVFIRST_M_B8 %x, 1, 0
...
---
name: vfirst_v_incompatible_emul
body: |
bb.0:
; CHECK-LABEL: name: vfirst_v_incompatible_emul
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
; CHECK-NEXT: %y:gpr = PseudoVFIRST_M_B16 %x, 1, 0 /* e8 */
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
%y:gpr = PseudoVFIRST_M_B16 %x, 1, 0
...
---
name: vcpop_v
body: |
bb.0:
; CHECK-LABEL: name: vcpop_v
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, 1, 0 /* e8 */
; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 /* e8 */
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
%y:gpr = PseudoVCPOP_M_B8 %x, 1, 0
...
---
name: vcopop_v_incompatible_eew
body: |
bb.0:
; CHECK-LABEL: name: vcopop_v_incompatible_eew
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B8 %x, 1, 0 /* e8 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0
%y:gpr = PseudoVCPOP_M_B8 %x, 1, 0
...
---
name: vcpop_v_incompaitble_emul
body: |
bb.0:
; CHECK-LABEL: name: vcpop_v_incompaitble_emul
; CHECK: %x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0 /* e8 */
; CHECK-NEXT: %y:gpr = PseudoVCPOP_M_B16 %x, 1, 0 /* e8 */
%x:vr = PseudoVMAND_MM_B8 $noreg, $noreg, -1, 0
%y:gpr = PseudoVCPOP_M_B16 %x, 1, 0
...
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