[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC #123799
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This holds a physical register unit or virtual register. Make the name more consistent with the RegUnit field it contains. I'm open to other name suggestions.
|
@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-llvm-regalloc Author: Craig Topper (topperc) ChangesThis holds a physical register unit or virtual register. Make the name more consistent with the RegUnit field it contains. I'm open to other name suggestions. Patch is 29.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/123799.diff 7 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index 3dd62b2ba333c3..7c1b31f82519a4 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -525,7 +525,7 @@ class ScheduleDAGMILive : public ScheduleDAGMI {
void initRegPressure();
- void updatePressureDiffs(ArrayRef<RegisterMaskPair> LiveUses);
+ void updatePressureDiffs(ArrayRef<RegUnitMaskPair> LiveUses);
void updateScheduledPressure(const SUnit *SU,
const std::vector<unsigned> &NewMaxPressure);
diff --git a/llvm/include/llvm/CodeGen/RegisterPressure.h b/llvm/include/llvm/CodeGen/RegisterPressure.h
index 8a46e505affd2f..d8ef85c13093fb 100644
--- a/llvm/include/llvm/CodeGen/RegisterPressure.h
+++ b/llvm/include/llvm/CodeGen/RegisterPressure.h
@@ -35,11 +35,11 @@ class MachineInstr;
class MachineRegisterInfo;
class RegisterClassInfo;
-struct RegisterMaskPair {
+struct RegUnitMaskPair {
Register RegUnit; ///< Virtual register or register unit.
LaneBitmask LaneMask;
- RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
+ RegUnitMaskPair(Register RegUnit, LaneBitmask LaneMask)
: RegUnit(RegUnit), LaneMask(LaneMask) {}
};
@@ -49,8 +49,8 @@ struct RegisterPressure {
std::vector<unsigned> MaxSetPressure;
/// List of live in virtual registers or physical register units.
- SmallVector<RegisterMaskPair,8> LiveInRegs;
- SmallVector<RegisterMaskPair,8> LiveOutRegs;
+ SmallVector<RegUnitMaskPair, 8> LiveInRegs;
+ SmallVector<RegUnitMaskPair, 8> LiveOutRegs;
void dump(const TargetRegisterInfo *TRI) const;
};
@@ -166,13 +166,13 @@ class PressureDiff {
class RegisterOperands {
public:
/// List of virtual registers and register units read by the instruction.
- SmallVector<RegisterMaskPair, 8> Uses;
+ SmallVector<RegUnitMaskPair, 8> Uses;
/// List of virtual registers and register units defined by the
/// instruction which are not dead.
- SmallVector<RegisterMaskPair, 8> Defs;
+ SmallVector<RegUnitMaskPair, 8> Defs;
/// List of virtual registers and register units defined by the
/// instruction but dead.
- SmallVector<RegisterMaskPair, 8> DeadDefs;
+ SmallVector<RegUnitMaskPair, 8> DeadDefs;
/// Analyze the given instruction \p MI and fill in the Uses, Defs and
/// DeadDefs list based on the MachineOperand flags.
@@ -185,7 +185,7 @@ class RegisterOperands {
void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
/// Use liveness information to find out which uses/defs are partially
- /// undefined/dead and adjust the RegisterMaskPairs accordingly.
+ /// undefined/dead and adjust the RegUnitMaskPairs accordingly.
/// If \p AddFlagsMI is given then missing read-undef and dead flags will be
/// added to the instruction.
void adjustLaneLiveness(const LiveIntervals &LIS,
@@ -303,7 +303,7 @@ class LiveRegSet {
/// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
/// Returns the previously live lanes of \p Pair.Reg.
- LaneBitmask insert(RegisterMaskPair Pair) {
+ LaneBitmask insert(RegUnitMaskPair Pair) {
unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
if (!InsertRes.second) {
@@ -316,7 +316,7 @@ class LiveRegSet {
/// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
/// Returns the previously live lanes of \p Pair.Reg.
- LaneBitmask erase(RegisterMaskPair Pair) {
+ LaneBitmask erase(RegUnitMaskPair Pair) {
unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
RegSet::iterator I = Regs.find(SparseIndex);
if (I == Regs.end())
@@ -330,12 +330,11 @@ class LiveRegSet {
return Regs.size();
}
- template<typename ContainerT>
- void appendTo(ContainerT &To) const {
+ void appendTo(SmallVectorImpl<RegUnitMaskPair> &To) const {
for (const IndexMaskPair &P : Regs) {
Register Reg = getRegFromSparseIndex(P.Index);
if (P.LaneMask.any())
- To.push_back(RegisterMaskPair(Reg, P.LaneMask));
+ To.emplace_back(Reg, P.LaneMask);
}
}
};
@@ -409,7 +408,7 @@ class RegPressureTracker {
/// Force liveness of virtual registers or physical register
/// units. Particularly useful to initialize the livein/out state of the
/// tracker before the first call to advance/recede.
- void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
+ void addLiveRegs(ArrayRef<RegUnitMaskPair> Regs);
/// Get the MI position corresponding to this register pressure.
MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
@@ -421,14 +420,14 @@ class RegPressureTracker {
void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
/// Recede across the previous instruction.
- void recede(SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
+ void recede(SmallVectorImpl<RegUnitMaskPair> *LiveUses = nullptr);
/// Recede across the previous instruction.
/// This "low-level" variant assumes that recedeSkipDebugValues() was
/// called previously and takes precomputed RegisterOperands for the
/// instruction.
void recede(const RegisterOperands &RegOpers,
- SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
+ SmallVectorImpl<RegUnitMaskPair> *LiveUses = nullptr);
/// Recede until we find an instruction which is not a DebugValue.
void recedeSkipDebugValues();
@@ -546,21 +545,21 @@ class RegPressureTracker {
protected:
/// Add Reg to the live out set and increase max pressure.
- void discoverLiveOut(RegisterMaskPair Pair);
+ void discoverLiveOut(RegUnitMaskPair Pair);
/// Add Reg to the live in set and increase max pressure.
- void discoverLiveIn(RegisterMaskPair Pair);
+ void discoverLiveIn(RegUnitMaskPair Pair);
/// Get the SlotIndex for the first nondebug instruction including or
/// after the current position.
SlotIndex getCurrSlot() const;
- void bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs);
+ void bumpDeadDefs(ArrayRef<RegUnitMaskPair> DeadDefs);
void bumpUpwardPressure(const MachineInstr *MI);
void bumpDownwardPressure(const MachineInstr *MI);
- void discoverLiveInOrOut(RegisterMaskPair Pair,
- SmallVectorImpl<RegisterMaskPair> &LiveInOrOut);
+ void discoverLiveInOrOut(RegUnitMaskPair Pair,
+ SmallVectorImpl<RegUnitMaskPair> &LiveInOrOut);
LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 54d9c1cf08e35b..76e21cfe72ff61 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -1981,7 +1981,7 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
NodeSet &NS) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
- SmallVector<RegisterMaskPair, 8> LiveOutRegs;
+ SmallVector<RegUnitMaskPair, 8> LiveOutRegs;
SmallSet<unsigned, 4> Uses;
for (SUnit *SU : NS) {
const MachineInstr *MI = SU->getInstr();
@@ -2002,13 +2002,11 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
Register Reg = MO.getReg();
if (Reg.isVirtual()) {
if (!Uses.count(Reg))
- LiveOutRegs.push_back(RegisterMaskPair(Reg,
- LaneBitmask::getNone()));
+ LiveOutRegs.emplace_back(Reg, LaneBitmask::getNone());
} else if (MRI.isAllocatable(Reg)) {
for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
if (!Uses.count(Unit))
- LiveOutRegs.push_back(
- RegisterMaskPair(Unit, LaneBitmask::getNone()));
+ LiveOutRegs.emplace_back(Unit, LaneBitmask::getNone());
}
}
RPTracker.addLiveRegs(LiveOutRegs);
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 91aaeea156c4a1..2ca553f14e81ce 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1288,7 +1288,7 @@ void ScheduleDAGMILive::initRegPressure() {
// Account for liveness generated by the region boundary.
if (LiveRegionEnd != RegionEnd) {
- SmallVector<RegisterMaskPair, 8> LiveUses;
+ SmallVector<RegUnitMaskPair, 8> LiveUses;
BotRPTracker.recede(&LiveUses);
updatePressureDiffs(LiveUses);
}
@@ -1353,8 +1353,8 @@ updateScheduledPressure(const SUnit *SU,
/// Update the PressureDiff array for liveness after scheduling this
/// instruction.
void ScheduleDAGMILive::updatePressureDiffs(
- ArrayRef<RegisterMaskPair> LiveUses) {
- for (const RegisterMaskPair &P : LiveUses) {
+ ArrayRef<RegUnitMaskPair> LiveUses) {
+ for (const RegUnitMaskPair &P : LiveUses) {
Register Reg = P.RegUnit;
/// FIXME: Currently assuming single-use physregs.
if (!Reg.isVirtual())
@@ -1579,7 +1579,7 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
unsigned MaxCyclicLatency = 0;
// Visit each live out vreg def to find def/use pairs that cross iterations.
- for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
+ for (const RegUnitMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
Register Reg = P.RegUnit;
if (!Reg.isVirtual())
continue;
@@ -1707,7 +1707,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
if (BotRPTracker.getPos() != CurrentBottom)
BotRPTracker.recedeSkipDebugValues();
- SmallVector<RegisterMaskPair, 8> LiveUses;
+ SmallVector<RegUnitMaskPair, 8> LiveUses;
BotRPTracker.recede(RegOpers, &LiveUses);
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(
diff --git a/llvm/lib/CodeGen/RegisterPressure.cpp b/llvm/lib/CodeGen/RegisterPressure.cpp
index 037986ec48afbc..0484eee438f5ea 100644
--- a/llvm/lib/CodeGen/RegisterPressure.cpp
+++ b/llvm/lib/CodeGen/RegisterPressure.cpp
@@ -95,7 +95,7 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
dbgs() << "Max Pressure: ";
dumpRegSetPressure(MaxSetPressure, TRI);
dbgs() << "Live In: ";
- for (const RegisterMaskPair &P : LiveInRegs) {
+ for (const RegUnitMaskPair &P : LiveInRegs) {
dbgs() << printVRegOrUnit(P.RegUnit, TRI);
if (!P.LaneMask.all())
dbgs() << ':' << PrintLaneMask(P.LaneMask);
@@ -103,7 +103,7 @@ void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
}
dbgs() << '\n';
dbgs() << "Live Out: ";
- for (const RegisterMaskPair &P : LiveOutRegs) {
+ for (const RegUnitMaskPair &P : LiveOutRegs) {
dbgs() << printVRegOrUnit(P.RegUnit, TRI);
if (!P.LaneMask.all())
dbgs() << ':' << PrintLaneMask(P.LaneMask);
@@ -358,7 +358,7 @@ void RegPressureTracker::closeRegion() {
void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
LiveThruPressure.assign(TRI->getNumRegPressureSets(), 0);
assert(isBottomClosed() && "need bottom-up tracking to intialize.");
- for (const RegisterMaskPair &Pair : P.LiveOutRegs) {
+ for (const RegUnitMaskPair &Pair : P.LiveOutRegs) {
Register RegUnit = Pair.RegUnit;
if (RegUnit.isVirtual() && !RPTracker.hasUntiedDef(RegUnit))
increaseSetPressure(LiveThruPressure, *MRI, RegUnit,
@@ -366,9 +366,9 @@ void RegPressureTracker::initLiveThru(const RegPressureTracker &RPTracker) {
}
}
-static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
+static LaneBitmask getRegLanes(ArrayRef<RegUnitMaskPair> RegUnits,
Register RegUnit) {
- auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegUnitMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I == RegUnits.end())
@@ -376,11 +376,11 @@ static LaneBitmask getRegLanes(ArrayRef<RegisterMaskPair> RegUnits,
return I->LaneMask;
}
-static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
- RegisterMaskPair Pair) {
+static void addRegLanes(SmallVectorImpl<RegUnitMaskPair> &RegUnits,
+ RegUnitMaskPair Pair) {
Register RegUnit = Pair.RegUnit;
assert(Pair.LaneMask.any());
- auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegUnitMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I == RegUnits.end()) {
@@ -390,23 +390,23 @@ static void addRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
}
}
-static void setRegZero(SmallVectorImpl<RegisterMaskPair> &RegUnits,
+static void setRegZero(SmallVectorImpl<RegUnitMaskPair> &RegUnits,
Register RegUnit) {
- auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegUnitMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I == RegUnits.end()) {
- RegUnits.push_back(RegisterMaskPair(RegUnit, LaneBitmask::getNone()));
+ RegUnits.emplace_back(RegUnit, LaneBitmask::getNone());
} else {
I->LaneMask = LaneBitmask::getNone();
}
}
-static void removeRegLanes(SmallVectorImpl<RegisterMaskPair> &RegUnits,
- RegisterMaskPair Pair) {
+static void removeRegLanes(SmallVectorImpl<RegUnitMaskPair> &RegUnits,
+ RegUnitMaskPair Pair) {
Register RegUnit = Pair.RegUnit;
assert(Pair.LaneMask.any());
- auto I = llvm::find_if(RegUnits, [RegUnit](const RegisterMaskPair Other) {
+ auto I = llvm::find_if(RegUnits, [RegUnit](const RegUnitMaskPair Other) {
return Other.RegUnit == RegUnit;
});
if (I != RegUnits.end()) {
@@ -480,7 +480,7 @@ class RegisterOperandsCollector {
collectOperand(*OperI);
// Remove redundant physreg dead defs.
- for (const RegisterMaskPair &P : RegOpers.Defs)
+ for (const RegUnitMaskPair &P : RegOpers.Defs)
removeRegLanes(RegOpers.DeadDefs, P);
}
@@ -489,7 +489,7 @@ class RegisterOperandsCollector {
collectOperandLanes(*OperI);
// Remove redundant physreg dead defs.
- for (const RegisterMaskPair &P : RegOpers.Defs)
+ for (const RegUnitMaskPair &P : RegOpers.Defs)
removeRegLanes(RegOpers.DeadDefs, P);
}
@@ -515,13 +515,12 @@ class RegisterOperandsCollector {
}
}
- void pushReg(Register Reg,
- SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
+ void pushReg(Register Reg, SmallVectorImpl<RegUnitMaskPair> &RegUnits) const {
if (Reg.isVirtual()) {
- addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneBitmask::getAll()));
+ addRegLanes(RegUnits, RegUnitMaskPair(Reg, LaneBitmask::getAll()));
} else if (MRI.isAllocatable(Reg)) {
for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
- addRegLanes(RegUnits, RegisterMaskPair(Unit, LaneBitmask::getAll()));
+ addRegLanes(RegUnits, RegUnitMaskPair(Unit, LaneBitmask::getAll()));
}
}
@@ -548,15 +547,15 @@ class RegisterOperandsCollector {
}
void pushRegLanes(Register Reg, unsigned SubRegIdx,
- SmallVectorImpl<RegisterMaskPair> &RegUnits) const {
+ SmallVectorImpl<RegUnitMaskPair> &RegUnits) const {
if (Reg.isVirtual()) {
LaneBitmask LaneMask = SubRegIdx != 0
? TRI.getSubRegIndexLaneMask(SubRegIdx)
: MRI.getMaxLaneMaskForVReg(Reg);
- addRegLanes(RegUnits, RegisterMaskPair(Reg, LaneMask));
+ addRegLanes(RegUnits, RegUnitMaskPair(Reg, LaneMask));
} else if (MRI.isAllocatable(Reg)) {
for (MCRegUnit Unit : TRI.regunits(Reg.asMCReg()))
- addRegLanes(RegUnits, RegisterMaskPair(Unit, LaneBitmask::getAll()));
+ addRegLanes(RegUnits, RegUnitMaskPair(Unit, LaneBitmask::getAll()));
}
}
};
@@ -622,7 +621,7 @@ void RegisterOperands::adjustLaneLiveness(const LiveIntervals &LIS,
LaneMask = getLiveLanesAt(LIS, MRI, true, RegUnit, Pos.getBaseIndex());
if (AddFlagsMI != nullptr) {
- for (const RegisterMaskPair &P : DeadDefs) {
+ for (const RegUnitMaskPair &P : DeadDefs) {
Register RegUnit = P.RegUnit;
if (!RegUnit.isVirtual())
continue;
@@ -651,10 +650,10 @@ void PressureDiffs::addInstruction(unsigned Idx,
const MachineRegisterInfo &MRI) {
PressureDiff &PDiff = (*this)[Idx];
assert(!PDiff.begin()->isValid() && "stale PDiff");
- for (const RegisterMaskPair &P : RegOpers.Defs)
+ for (const RegUnitMaskPair &P : RegOpers.Defs)
PDiff.addPressureChange(P.RegUnit, true, &MRI);
- for (const RegisterMaskPair &P : RegOpers.Uses)
+ for (const RegUnitMaskPair &P : RegOpers.Uses)
PDiff.addPressureChange(P.RegUnit, false, &MRI);
}
@@ -694,20 +693,20 @@ void PressureDiff::addPressureChange(Register RegUnit, bool IsDec,
}
/// Force liveness of registers.
-void RegPressureTracker::addLiveRegs(ArrayRef<RegisterMaskPair> Regs) {
- for (const RegisterMaskPair &P : Regs) {
+void RegPressureTracker::addLiveRegs(ArrayRef<RegUnitMaskPair> Regs) {
+ for (const RegUnitMaskPair &P : Regs) {
LaneBitmask PrevMask = LiveRegs.insert(P);
LaneBitmask NewMask = PrevMask | P.LaneMask;
increaseRegPressure(P.RegUnit, PrevMask, NewMask);
}
}
-void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
- SmallVectorImpl<RegisterMaskPair> &LiveInOrOut) {
+void RegPressureTracker::discoverLiveInOrOut(
+ RegUnitMaskPair Pair, SmallVectorImpl<RegUnitMaskPair> &LiveInOrOut) {
assert(Pair.LaneMask.any());
Register RegUnit = Pair.RegUnit;
- auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegisterMaskPair &Other) {
+ auto I = llvm::find_if(LiveInOrOut, [RegUnit](const RegUnitMaskPair &Other) {
return Other.RegUnit == RegUnit;
});
LaneBitmask PrevMask;
@@ -724,22 +723,22 @@ void RegPressureTracker::discoverLiveInOrOut(RegisterMaskPair Pair,
increaseSetPressure(P.MaxSetPressure, *MRI, RegUnit, PrevMask, NewMask);
}
-void RegPressureTracker::discoverLiveIn(RegisterMaskPair Pair) {
+void RegPressureTracker::discoverLiveIn(RegUnitMaskPair Pair) {
discoverLiveInOrOut(Pair, P.LiveInRegs);
}
-void RegPressureTracker::discoverLiveOut(RegisterMaskPair Pair) {
+void RegPressureTracker::discoverLiveOut(RegUnitMaskPair Pair) {
discoverLiveInOrOut(Pair, P.LiveOutRegs);
}
-void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
- for (const RegisterMaskPair &P : DeadDefs) {
+void RegPressureTracker::bumpDeadDefs(ArrayRef<RegUnitMaskPair> DeadDefs) {
+ for (const RegUnitMaskPair &P : DeadDefs) {
Register Reg = P.RegUnit;
LaneBitmask LiveMask = LiveRegs.contains(Reg);
LaneBitmask BumpedMask = LiveMask | P.LaneMask;
increaseRegPressure(Reg, LiveMask, BumpedMask);
}
- for (const RegisterMaskPair &P : DeadDefs) {
+ for (const RegUnitMaskPair &P : DeadDefs) {
Register Reg = P.RegUnit;
LaneBitmask LiveMask = LiveRegs.contains(Reg);
LaneBitmask BumpedMask = LiveMask | P.LaneMask;
@@ -753,7 +752,7 @@ void RegPressureTracker::bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs) {
/// difference pointer is provided record the changes is pressure caused by this
/// instruction independent of liveness.
void RegPressureTracker::recede(const RegisterOperands &RegOpers,
- SmallVectorImpl<RegisterMaskPair> *LiveUses) {
+ SmallVectorImpl<RegUnitMaskPair> *LiveUses) {
assert(!CurrPos->isDebugOrPseudoInstr());
// Boost pressure for all dead defs together.
@@ -761,7 +760,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
// Kill liveness at live defs.
// TODO: consider earlyclobbers?
- for (const RegisterMaskPair &Def : RegOpers.Defs) {
+ for (const RegUnitMaskPair &Def : RegOpers.Defs) {
Register Reg = Def.RegUnit;
LaneBitmask PreviousMask = LiveRegs.erase(Def);
@@ -769,7 +768,7 @@ void RegPressureTracker::recede(const RegisterOperands &RegOpers,
LaneBitmask LiveOut = Def.LaneMask &...
[truncated]
|
topperc
commented
Jan 21, 2025
| @@ -330,12 +330,11 @@ class LiveRegSet { | |||
| return Regs.size(); | |||
| } | |||
|
|
|||
| template<typename ContainerT> | |||
| void appendTo(ContainerT &To) const { | |||
| void appendTo(SmallVectorImpl<RegUnitMaskPair> &To) const { | |||
There was a problem hiding this comment.
I removed the template here in favor of SmallVectorImpl&
(just to suggest something) |
arsenm
reviewed
Jan 22, 2025
| Register RegUnit; ///< Virtual register or register unit. | ||
| LaneBitmask LaneMask; | ||
|
|
||
| RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask) | ||
| RegUnitMaskPair(Register RegUnit, LaneBitmask LaneMask) | ||
| : RegUnit(RegUnit), LaneMask(LaneMask) {} |
There was a problem hiding this comment.
This is really something like std::variant<unsigned RegUnit, std::pair<Register, LaneBitmask>>.
Maybe LiveInReg? That's all this is used for I believe
There was a problem hiding this comment.
It seems to be used throughout the RegisterPressure code for more than just live ins.
arsenm
reviewed
Jan 22, 2025
| @@ -35,11 +35,11 @@ class MachineInstr; | |||
| class MachineRegisterInfo; | |||
| class RegisterClassInfo; | |||
|
|
|||
| struct RegUnitMaskPair { | |||
| struct VRegOrUnitMaskPair { | |||
There was a problem hiding this comment.
The mask is really paired with the VReg, VRegMaskOrUnit?
There was a problem hiding this comment.
Ok. I was debating whether I should keep "VRegOrUnit" together to match the suggested name from #123768 (comment)
I'll change it.
topperc
changed the title
arsenm
approved these changes
Jan 22, 2025
| @@ -35,11 +35,11 @@ class MachineInstr; | |||
| class MachineRegisterInfo; | |||
| class RegisterClassInfo; | |||
|
|
|||
| struct VRegOrUnitMaskPair { | |||
| struct VRegMaskOrUnitPair { | |||
There was a problem hiding this comment.
Doesn't really need the pair in the name. The pair is the VReg+Mask part
arsenm
approved these changes
Jan 22, 2025
topperc
changed the title
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This holds a physical register unit or virtual register. Make the name more consistent with the RegUnit field it contains.
I'm open to other name suggestions.
While I was here I've used emplace_back and removed an unneeded use of a template.