Skip to content

[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC #123799

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Jan 22, 2025
Merged

[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC #123799

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
d8285bd
[CodeGen] Rename RegisterMaskPair to RegUnitMaskPair. NFC
topperc Jan 21, 2025
420a2cb
fixup! Rename to VRegOrUnitMaskPair.
topperc Jan 22, 2025
3ed3c8f
fixup! Use VRegMaskOrUnitPair
topperc Jan 22, 2025
eb94888
fixup! Drop Pair
topperc Jan 22, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion llvm/include/llvm/CodeGen/MachineScheduler.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -525,7 +525,7 @@ class ScheduleDAGMILive : public ScheduleDAGMI {

void initRegPressure();

void updatePressureDiffs(ArrayRef<RegisterMaskPair> LiveUses);
void updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses);

void updateScheduledPressure(const SUnit *SU,
const std::vector<unsigned> &NewMaxPressure);
Expand Down
41 changes: 20 additions & 21 deletions llvm/include/llvm/CodeGen/RegisterPressure.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,11 @@ class MachineInstr;
class MachineRegisterInfo;
class RegisterClassInfo;

struct RegisterMaskPair {
struct VRegMaskOrUnit {
Register RegUnit; ///< Virtual register or register unit.
LaneBitmask LaneMask;

RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
VRegMaskOrUnit(Register RegUnit, LaneBitmask LaneMask)
: RegUnit(RegUnit), LaneMask(LaneMask) {}
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This is really something like std::variant<unsigned RegUnit, std::pair<Register, LaneBitmask>>.

Maybe LiveInReg? That's all this is used for I believe

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

It seems to be used throughout the RegisterPressure code for more than just live ins.

};

Expand All @@ -49,8 +49,8 @@ struct RegisterPressure {
std::vector<unsigned> MaxSetPressure;

/// List of live in virtual registers or physical register units.
SmallVector<RegisterMaskPair,8> LiveInRegs;
SmallVector<RegisterMaskPair,8> LiveOutRegs;
SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;

void dump(const TargetRegisterInfo *TRI) const;
};
Expand Down Expand Up @@ -166,13 +166,13 @@ class PressureDiff {
class RegisterOperands {
public:
/// List of virtual registers and register units read by the instruction.
SmallVector<RegisterMaskPair, 8> Uses;
SmallVector<VRegMaskOrUnit, 8> Uses;
/// List of virtual registers and register units defined by the
/// instruction which are not dead.
SmallVector<RegisterMaskPair, 8> Defs;
SmallVector<VRegMaskOrUnit, 8> Defs;
/// List of virtual registers and register units defined by the
/// instruction but dead.
SmallVector<RegisterMaskPair, 8> DeadDefs;
SmallVector<VRegMaskOrUnit, 8> DeadDefs;

/// Analyze the given instruction \p MI and fill in the Uses, Defs and
/// DeadDefs list based on the MachineOperand flags.
Expand All @@ -185,7 +185,7 @@ class RegisterOperands {
void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);

/// Use liveness information to find out which uses/defs are partially
/// undefined/dead and adjust the RegisterMaskPairs accordingly.
/// undefined/dead and adjust the VRegMaskOrUnits accordingly.
/// If \p AddFlagsMI is given then missing read-undef and dead flags will be
/// added to the instruction.
void adjustLaneLiveness(const LiveIntervals &LIS,
Expand Down Expand Up @@ -303,7 +303,7 @@ class LiveRegSet {

/// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
/// Returns the previously live lanes of \p Pair.Reg.
LaneBitmask insert(RegisterMaskPair Pair) {
LaneBitmask insert(VRegMaskOrUnit Pair) {
unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
if (!InsertRes.second) {
Expand All @@ -316,7 +316,7 @@ class LiveRegSet {

/// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
/// Returns the previously live lanes of \p Pair.Reg.
LaneBitmask erase(RegisterMaskPair Pair) {
LaneBitmask erase(VRegMaskOrUnit Pair) {
unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
RegSet::iterator I = Regs.find(SparseIndex);
if (I == Regs.end())
Expand All @@ -330,12 +330,11 @@ class LiveRegSet {
return Regs.size();
}

template<typename ContainerT>
void appendTo(ContainerT &To) const {
void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
for (const IndexMaskPair &P : Regs) {
Register Reg = getRegFromSparseIndex(P.Index);
if (P.LaneMask.any())
To.push_back(RegisterMaskPair(Reg, P.LaneMask));
To.emplace_back(Reg, P.LaneMask);
}
}
};
Expand Down Expand Up @@ -409,7 +408,7 @@ class RegPressureTracker {
/// Force liveness of virtual registers or physical register
/// units. Particularly useful to initialize the livein/out state of the
/// tracker before the first call to advance/recede.
void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);

/// Get the MI position corresponding to this register pressure.
MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
Expand All @@ -421,14 +420,14 @@ class RegPressureTracker {
void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }

/// Recede across the previous instruction.
void recede(SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);

/// Recede across the previous instruction.
/// This "low-level" variant assumes that recedeSkipDebugValues() was
/// called previously and takes precomputed RegisterOperands for the
/// instruction.
void recede(const RegisterOperands &RegOpers,
SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);

/// Recede until we find an instruction which is not a DebugValue.
void recedeSkipDebugValues();
Expand Down Expand Up @@ -546,21 +545,21 @@ class RegPressureTracker {

protected:
/// Add Reg to the live out set and increase max pressure.
void discoverLiveOut(RegisterMaskPair Pair);
void discoverLiveOut(VRegMaskOrUnit Pair);
/// Add Reg to the live in set and increase max pressure.
void discoverLiveIn(RegisterMaskPair Pair);
void discoverLiveIn(VRegMaskOrUnit Pair);

/// Get the SlotIndex for the first nondebug instruction including or
/// after the current position.
SlotIndex getCurrSlot() const;

void bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs);
void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);

void bumpUpwardPressure(const MachineInstr *MI);
void bumpDownwardPressure(const MachineInstr *MI);

void discoverLiveInOrOut(RegisterMaskPair Pair,
SmallVectorImpl<RegisterMaskPair> &LiveInOrOut);
void discoverLiveInOrOut(VRegMaskOrUnit Pair,
SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);

LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;
Expand Down
8 changes: 3 additions & 5 deletions llvm/lib/CodeGen/MachinePipeliner.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1981,7 +1981,7 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
NodeSet &NS) {
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<RegisterMaskPair, 8> LiveOutRegs;
SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
SmallSet<unsigned, 4> Uses;
for (SUnit *SU : NS) {
const MachineInstr *MI = SU->getInstr();
Expand All @@ -2002,13 +2002,11 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
Register Reg = MO.getReg();
if (Reg.isVirtual()) {
if (!Uses.count(Reg))
LiveOutRegs.push_back(RegisterMaskPair(Reg,
LaneBitmask::getNone()));
LiveOutRegs.emplace_back(Reg, LaneBitmask::getNone());
} else if (MRI.isAllocatable(Reg)) {
for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
if (!Uses.count(Unit))
LiveOutRegs.push_back(
RegisterMaskPair(Unit, LaneBitmask::getNone()));
LiveOutRegs.emplace_back(Unit, LaneBitmask::getNone());
}
}
RPTracker.addLiveRegs(LiveOutRegs);
Expand Down
11 changes: 5 additions & 6 deletions llvm/lib/CodeGen/MachineScheduler.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1288,7 +1288,7 @@ void ScheduleDAGMILive::initRegPressure() {

// Account for liveness generated by the region boundary.
if (LiveRegionEnd != RegionEnd) {
SmallVector<RegisterMaskPair, 8> LiveUses;
SmallVector<VRegMaskOrUnit, 8> LiveUses;
BotRPTracker.recede(&LiveUses);
updatePressureDiffs(LiveUses);
}
Expand Down Expand Up @@ -1352,9 +1352,8 @@ updateScheduledPressure(const SUnit *SU,

/// Update the PressureDiff array for liveness after scheduling this
/// instruction.
void ScheduleDAGMILive::updatePressureDiffs(
ArrayRef<RegisterMaskPair> LiveUses) {
for (const RegisterMaskPair &P : LiveUses) {
void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
for (const VRegMaskOrUnit &P : LiveUses) {
Register Reg = P.RegUnit;
/// FIXME: Currently assuming single-use physregs.
if (!Reg.isVirtual())
Expand Down Expand Up @@ -1579,7 +1578,7 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {

unsigned MaxCyclicLatency = 0;
// Visit each live out vreg def to find def/use pairs that cross iterations.
for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
for (const VRegMaskOrUnit &P : RPTracker.getPressure().LiveOutRegs) {
Register Reg = P.RegUnit;
if (!Reg.isVirtual())
continue;
Expand Down Expand Up @@ -1707,7 +1706,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {

if (BotRPTracker.getPos() != CurrentBottom)
BotRPTracker.recedeSkipDebugValues();
SmallVector<RegisterMaskPair, 8> LiveUses;
SmallVector<VRegMaskOrUnit, 8> LiveUses;
BotRPTracker.recede(RegOpers, &LiveUses);
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(
Expand Down
Loading
Loading