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[msan][NFCI] Add tests for sum long across vector #125761

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Feb 4, 2025
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[msan][NFCI] Add tests for sum long across vector #125761

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64 changes: 64 additions & 0 deletions llvm/test/Instrumentation/MemorySanitizer/AArch64/arm64-vaddlv.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt < %s -passes=msan -S | FileCheck %s
;
; Forked from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll
;
; Currently handled (suboptimally) by handleUnknownInstruction:
; - llvm.aarch64.neon.saddlv
; - llvm.aarch64.neon.uaddlv

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--linux-android9001"

define i64 @test_vaddlv_s32(<2 x i32> %a1) nounwind readnone #0 {
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why is the test name different to the intrinsic name?

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@thurstond thurstond Feb 4, 2025 •
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This is cloned from llvm/test/CodeGen/AArch64/arm64-vaddlv.ll so I don't know for sure, but my guess is:

  • they adopted a convention of "arm64-v" as the filename, to denote vector instructions
  • internally, they use the filename for the test names (and append "_s" or "_u" for signed/unsigned)

; CHECK-LABEL: define i64 @test_vaddlv_s32(
; CHECK-SAME: <2 x i32> [[A1:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1:![0-9]+]]
; CHECK: 2:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]]
; CHECK-NEXT: unreachable
; CHECK: 3:
; CHECK-NEXT: [[VADDLV_I:%.*]] = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> [[A1]]) #[[ATTR2:[0-9]+]]
; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i64 [[VADDLV_I]]
;
entry:
%vaddlv.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %a1) nounwind
ret i64 %vaddlv.i
}

define i64 @test_vaddlv_u32(<2 x i32> %a1) nounwind readnone #0 {
; CHECK-LABEL: define i64 @test_vaddlv_u32(
; CHECK-SAME: <2 x i32> [[A1:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to i64
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]
; CHECK: 2:
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]
; CHECK-NEXT: unreachable
; CHECK: 3:
; CHECK-NEXT: [[VADDLV_I:%.*]] = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32> [[A1]]) #[[ATTR2]]
; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 8
; CHECK-NEXT: ret i64 [[VADDLV_I]]
;
entry:
%vaddlv.i = tail call i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32> %a1) nounwind
ret i64 %vaddlv.i
}

declare i64 @llvm.aarch64.neon.uaddlv.i64.v2i32(<2 x i32>) nounwind readnone

declare i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32>) nounwind readnone

attributes #0 = { sanitize_memory }
;.
; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
;.