[CodeGen][NPM] Port ExpandPostRAPseudos to NPM

llvm/include/llvm/CodeGen/ExpandPostRAPseudos.h

@@ -0,0 +1,24 @@
+//===- llvm/CodeGen/ExpandPostRAPseudos.h --------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_EXPANDPOSTRAPSEUDOS_H
+#define LLVM_CODEGEN_EXPANDPOSTRAPSEUDOS_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class ExpandPostRAPseudosPass : public PassInfoMixin<ExpandPostRAPseudosPass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_EXPANDPOSTRAPSEUDOS_H

llvm/include/llvm/InitializePasses.h

@@ -108,7 +108,7 @@ void initializeEHContGuardCatchretPass(PassRegistry &);
 void initializeExpandLargeFpConvertLegacyPassPass(PassRegistry &);
 void initializeExpandLargeDivRemLegacyPassPass(PassRegistry &);
 void initializeExpandMemCmpLegacyPassPass(PassRegistry &);
-void initializeExpandPostRAPass(PassRegistry &);
+void initializeExpandPostRALegacyPass(PassRegistry &);
 void initializeExpandReductionsPass(PassRegistry &);
 void initializeExpandVariadicsPass(PassRegistry &);
 void initializeExternalAAWrapperPassPass(PassRegistry &);

llvm/include/llvm/Passes/CodeGenPassBuilder.h

@@ -31,6 +31,7 @@
 #include "llvm/CodeGen/ExpandLargeDivRem.h"
 #include "llvm/CodeGen/ExpandLargeFpConvert.h"
 #include "llvm/CodeGen/ExpandMemCmp.h"
+#include "llvm/CodeGen/ExpandPostRAPseudos.h"
 #include "llvm/CodeGen/ExpandReductions.h"
 #include "llvm/CodeGen/FinalizeISel.h"
 #include "llvm/CodeGen/GCMetadata.h"

llvm/include/llvm/Passes/MachinePassRegistry.def

@@ -154,6 +154,7 @@ MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
 MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
 MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
 MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
+MACHINE_FUNCTION_PASS("post-ra-pseudos", ExpandPostRAPseudosPass())
 MACHINE_FUNCTION_PASS("print", PrintMIRPass())
 MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs()))
@@ -271,7 +272,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
 DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
 DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
 DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
-DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
 DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass)
 DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
 DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)

llvm/lib/CodeGen/CodeGen.cpp

@@ -42,7 +42,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeExpandLargeDivRemLegacyPassPass(Registry);
   initializeExpandLargeFpConvertLegacyPassPass(Registry);
   initializeExpandMemCmpLegacyPassPass(Registry);
-  initializeExpandPostRAPass(Registry);
+  initializeExpandPostRALegacyPass(Registry);
   initializeFEntryInserterPass(Registry);
   initializeFinalizeISelPass(Registry);
   initializeFinalizeMachineBundlesPass(Registry);

llvm/lib/CodeGen/ExpandPostRAPseudos.cpp

@@ -11,8 +11,11 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/CodeGen/ExpandPostRAPseudos.h"
+#include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -26,14 +29,21 @@ using namespace llvm;
 #define DEBUG_TYPE "postrapseudos"
 
 namespace {
-struct ExpandPostRA : public MachineFunctionPass {
+struct ExpandPostRA {
+  bool run(MachineFunction &);
+
 private:
   const TargetRegisterInfo *TRI = nullptr;
   const TargetInstrInfo *TII = nullptr;
 
-public:
-  static char ID; // Pass identification, replacement for typeid
-  ExpandPostRA() : MachineFunctionPass(ID) {}
+  bool LowerSubregToReg(MachineInstr *MI);
+};
+
+struct ExpandPostRALegacy : public MachineFunctionPass {
+  static char ID;
+  ExpandPostRALegacy() : MachineFunctionPass(ID) {
+    initializeExpandPostRALegacyPass(*PassRegistry::getPassRegistry());
+  }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
@@ -43,17 +53,26 @@ struct ExpandPostRA : public MachineFunctionPass {
   }
 
   /// runOnMachineFunction - pass entry point
-  bool runOnMachineFunction(MachineFunction&) override;
-
-private:
-  bool LowerSubregToReg(MachineInstr *MI);
+  bool runOnMachineFunction(MachineFunction &) override;
 };
 } // end anonymous namespace
 
-char ExpandPostRA::ID = 0;
-char &llvm::ExpandPostRAPseudosID = ExpandPostRA::ID;
+PreservedAnalyses
+ExpandPostRAPseudosPass::run(MachineFunction &MF,
+                             MachineFunctionAnalysisManager &MFAM) {
+  if (!ExpandPostRA().run(MF))
+    return PreservedAnalyses::all();
+
+  return getMachineFunctionPassPreservedAnalyses()
+      .preserveSet<CFGAnalyses>()
+      .preserve<MachineLoopAnalysis>()
+      .preserve<MachineDominatorTreeAnalysis>();
+}
+
+char ExpandPostRALegacy::ID = 0;
+char &llvm::ExpandPostRAPseudosID = ExpandPostRALegacy::ID;
 
-INITIALIZE_PASS(ExpandPostRA, DEBUG_TYPE,
+INITIALIZE_PASS(ExpandPostRALegacy, DEBUG_TYPE,
                 "Post-RA pseudo instruction expansion pass", false, false)
 
 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
@@ -115,10 +134,14 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
   return true;
 }
 
+bool ExpandPostRALegacy::runOnMachineFunction(MachineFunction &MF) {
+  return ExpandPostRA().run(MF);
+}
+
 /// runOnMachineFunction - Reduce subregister inserts and extracts to register
 /// copies.
 ///
-bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
+bool ExpandPostRA::run(MachineFunction &MF) {
   LLVM_DEBUG(dbgs() << "Machine Function\n"
                     << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
                     << "********** Function: " << MF.getName() << '\n');

llvm/lib/Passes/PassBuilder.cpp

@@ -90,6 +90,7 @@
 #include "llvm/CodeGen/ExpandLargeDivRem.h"
 #include "llvm/CodeGen/ExpandLargeFpConvert.h"
 #include "llvm/CodeGen/ExpandMemCmp.h"
+#include "llvm/CodeGen/ExpandPostRAPseudos.h"
 #include "llvm/CodeGen/FinalizeISel.h"
 #include "llvm/CodeGen/GCMetadata.h"
 #include "llvm/CodeGen/GlobalMerge.h"

llvm/test/CodeGen/AArch64/seqpaircopy.mir

@@ -1,4 +1,5 @@
 # RUN: llc -o - %s -mtriple=aarch64-- -mattr=+v8.1a -run-pass=postrapseudos | FileCheck %s
+# RUN: llc -o - %s -mtriple=aarch64-- -mattr=+v8.1a -passes=post-ra-pseudos | FileCheck %s
 ---
 # CHECK-LABEL: name: copy_xseqpairs
 name: copy_xseqpairs

llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir

@@ -3,6 +3,8 @@
 # RUN: llc -mtriple=amdgcn -mcpu=gfx90a -run-pass postrapseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX90A %s
 # RUN: llc -mtriple=amdgcn -mcpu=gfx942 -run-pass postrapseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX942 %s
 
+# RUN: llc -mtriple=amdgcn -mcpu=gfx942 -passes=post-ra-pseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX942 %s
+
 --- |
     define amdgpu_kernel void @a_to_v() #0 { ret void }
     define amdgpu_kernel void @a2_to_v2() #0 { ret void }

llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -verify-machineinstrs -mtriple riscv64 -run-pass=postrapseudos %s -o - | FileCheck %s
+# RUN: llc -verify-machineinstrs -mtriple riscv64 -passes=post-ra-pseudos %s -o - | FileCheck %s
 
 ...
 ---

llvm/test/CodeGen/SystemZ/copy-phys-reg-gr64-to-fp64.mir

@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
 # RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -run-pass=postrapseudos -o - %s | FileCheck %s
+# RUN: llc -mtriple=s390x-ibm-linux -mcpu=z13 -passes=post-ra-pseudos -o - %s | FileCheck %s
 ---
 name:            copy_fp64_to_gr64__f3d_to_r1d
 tracksRegLiveness: true