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Merged
merged 1 commit into from
Mar 7, 2025
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[MachinePipeliner] Use Register. NFC #130165

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10 changes: 5 additions & 5 deletions llvm/include/llvm/CodeGen/MachinePipeliner.h
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Original file line number Diff line number Diff line change
Expand Up @@ -269,7 +269,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;

/// Instructions to change when emitting the final schedule.
DenseMap<SUnit *, std::pair<unsigned, int64_t>> InstrChanges;
DenseMap<SUnit *, std::pair<Register, int64_t>> InstrChanges;

/// We may create a new instruction, so remember it because it
/// must be deleted when the pass is finished.
Expand Down Expand Up @@ -374,12 +374,12 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {

/// Return the new base register that was stored away for the changed
/// instruction.
unsigned getInstrBaseReg(SUnit *SU) const {
DenseMap<SUnit *, std::pair<unsigned, int64_t>>::const_iterator It =
Register getInstrBaseReg(SUnit *SU) const {
DenseMap<SUnit *, std::pair<Register, int64_t>>::const_iterator It =
InstrChanges.find(SU);
if (It != InstrChanges.end())
return It->second.first;
return 0;
return Register();
}

void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
Expand Down Expand Up @@ -415,7 +415,7 @@ class SwingSchedulerDAG : public ScheduleDAGInstrs {
bool computeDelta(const MachineInstr &MI, int &Delta) const;
MachineInstr *findDefInLoop(Register Reg);
bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos,
unsigned &OffsetPos, unsigned &NewBase,
unsigned &OffsetPos, Register &NewBase,
int64_t &NewOffset);
void postProcessDAG();
/// Set the Minimum Initiation Interval for this schedule attempt.
Expand Down
20 changes: 10 additions & 10 deletions llvm/include/llvm/CodeGen/ModuloSchedule.h
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Original file line number Diff line number Diff line change
Expand Up @@ -160,10 +160,10 @@ class ModuloSchedule {
/// rewriting the old loop and inserting prologs and epilogs as required.
class ModuloScheduleExpander {
public:
using InstrChangesTy = DenseMap<MachineInstr *, std::pair<unsigned, int64_t>>;
using InstrChangesTy = DenseMap<MachineInstr *, std::pair<Register, int64_t>>;

private:
using ValueMapTy = DenseMap<unsigned, unsigned>;
using ValueMapTy = DenseMap<Register, Register>;
using MBBVectorTy = SmallVectorImpl<MachineBasicBlock *>;
using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;

Expand All @@ -183,7 +183,7 @@ class ModuloScheduleExpander {
/// The first element in the pair is the max difference in stages. The
/// second is true if the register defines a Phi value and loop value is
/// scheduled before the Phi.
std::map<unsigned, std::pair<unsigned, bool>> RegToStageDiff;
std::map<Register, std::pair<unsigned, bool>> RegToStageDiff;

/// Instructions to change when emitting the final schedule.
InstrChangesTy InstrChanges;
Expand Down Expand Up @@ -221,21 +221,21 @@ class ModuloScheduleExpander {
void updateInstruction(MachineInstr *NewMI, bool LastDef,
unsigned CurStageNum, unsigned InstrStageNum,
ValueMapTy *VRMap);
MachineInstr *findDefInLoop(unsigned Reg);
unsigned getPrevMapVal(unsigned StageNum, unsigned PhiStage, unsigned LoopVal,
MachineInstr *findDefInLoop(Register Reg);
Register getPrevMapVal(unsigned StageNum, unsigned PhiStage, Register LoopVal,
unsigned LoopStage, ValueMapTy *VRMap,
MachineBasicBlock *BB);
void rewritePhiValues(MachineBasicBlock *NewBB, unsigned StageNum,
ValueMapTy *VRMap, InstrMapTy &InstrMap);
void rewriteScheduledInstr(MachineBasicBlock *BB, InstrMapTy &InstrMap,
unsigned CurStageNum, unsigned PhiNum,
MachineInstr *Phi, unsigned OldReg,
unsigned NewReg, unsigned PrevReg = 0);
MachineInstr *Phi, Register OldReg,
Register NewReg, Register PrevReg = Register());
bool isLoopCarried(MachineInstr &Phi);

/// Return the max. number of stages/iterations that can occur between a
/// register definition and its uses.
unsigned getStagesForReg(int Reg, unsigned CurStage) {
unsigned getStagesForReg(Register Reg, unsigned CurStage) {
std::pair<unsigned, bool> Stages = RegToStageDiff[Reg];
if ((int)CurStage > Schedule.getNumStages() - 1 && Stages.first == 0 &&
Stages.second)
Expand All @@ -249,7 +249,7 @@ class ModuloScheduleExpander {
/// This is not the case if the loop value is scheduled prior to the
/// Phi in the same stage. This function returns the number of stages
/// or iterations needed between the Phi definition and any uses.
unsigned getStagesForPhi(int Reg) {
unsigned getStagesForPhi(Register Reg) {
std::pair<unsigned, bool> Stages = RegToStageDiff[Reg];
if (Stages.second)
return Stages.first;
Expand Down Expand Up @@ -374,7 +374,7 @@ class PeelingModuloScheduleExpander {
/// It unrolls the kernel enough to avoid overlap of register lifetime.
class ModuloScheduleExpanderMVE {
private:
using ValueMapTy = DenseMap<unsigned, unsigned>;
using ValueMapTy = DenseMap<Register, Register>;
using MBBVectorTy = SmallVectorImpl<MachineBasicBlock *>;
using InstrMapTy = DenseMap<MachineInstr *, MachineInstr *>;

Expand Down
59 changes: 30 additions & 29 deletions llvm/lib/CodeGen/MachinePipeliner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -710,7 +710,7 @@ void SwingSchedulerDAG::schedule() {
Stages[SU->getInstr()] = Schedule.stageScheduled(SU);
}
}
DenseMap<MachineInstr *, std::pair<unsigned, int64_t>> NewInstrChanges;
DenseMap<MachineInstr *, std::pair<Register, int64_t>> NewInstrChanges;
for (auto &KV : NewMIs) {
Cycles[KV.first] = Cycles[KV.second];
Stages[KV.first] = Stages[KV.second];
Expand Down Expand Up @@ -756,27 +756,27 @@ void SwingSchedulerDAG::finishBlock() {
/// Return the register values for the operands of a Phi instruction.
/// This function assume the instruction is a Phi.
static void getPhiRegs(MachineInstr &Phi, MachineBasicBlock *Loop,
unsigned &InitVal, unsigned &LoopVal) {
Register &InitVal, Register &LoopVal) {
assert(Phi.isPHI() && "Expecting a Phi.");

InitVal = 0;
LoopVal = 0;
InitVal = Register();
LoopVal = Register();
for (unsigned i = 1, e = Phi.getNumOperands(); i != e; i += 2)
if (Phi.getOperand(i + 1).getMBB() != Loop)
InitVal = Phi.getOperand(i).getReg();
else
LoopVal = Phi.getOperand(i).getReg();

assert(InitVal != 0 && LoopVal != 0 && "Unexpected Phi structure.");
assert(InitVal && LoopVal && "Unexpected Phi structure.");
}

/// Return the Phi register value that comes the loop block.
static unsigned getLoopPhiReg(const MachineInstr &Phi,
static Register getLoopPhiReg(const MachineInstr &Phi,
const MachineBasicBlock *LoopBB) {
for (unsigned i = 1, e = Phi.getNumOperands(); i != e; i += 2)
if (Phi.getOperand(i + 1).getMBB() == LoopBB)
return Phi.getOperand(i).getReg();
return 0;
return Register();
}

/// Return true if SUb can be reached from SUa following the chain edges.
Expand Down Expand Up @@ -937,8 +937,8 @@ void SwingSchedulerDAG::updatePhiDependences() {
for (SUnit &I : SUnits) {
RemoveDeps.clear();
// Set to true if the instruction has an operand defined by a Phi.
unsigned HasPhiUse = 0;
unsigned HasPhiDef = 0;
Register HasPhiUse;
Register HasPhiDef;
MachineInstr *MI = I.getInstr();
// Iterate over each operand, and we process the definitions.
for (const MachineOperand &MO : MI->operands()) {
Expand Down Expand Up @@ -1017,7 +1017,8 @@ void SwingSchedulerDAG::changeDependences() {
// If so, we update the base and offset of the instruction and change
// the dependences.
for (SUnit &I : SUnits) {
unsigned BasePos = 0, OffsetPos = 0, NewBase = 0;
unsigned BasePos = 0, OffsetPos = 0;
Register NewBase;
int64_t NewOffset = 0;
if (!canUseLastOffsetValue(I.getInstr(), BasePos, OffsetPos, NewBase,
NewOffset))
Expand Down Expand Up @@ -1982,7 +1983,7 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
SmallSet<unsigned, 4> Uses;
SmallSet<Register, 4> Uses;
for (SUnit *SU : NS) {
const MachineInstr *MI = SU->getInstr();
if (MI->isPHI())
Expand Down Expand Up @@ -2646,7 +2647,7 @@ bool SwingSchedulerDAG::computeDelta(const MachineInstr &MI, int &Delta) const {
bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI,
unsigned &BasePos,
unsigned &OffsetPos,
unsigned &NewBase,
Register &NewBase,
int64_t &Offset) {
// Get the load instruction.
if (TII->isPostIncrement(*MI))
Expand All @@ -2662,7 +2663,7 @@ bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI,
if (!Phi || !Phi->isPHI())
return false;
// Get the register defined in the loop block.
unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent());
Register PrevReg = getLoopPhiReg(*Phi, MI->getParent());
if (!PrevReg)
return false;

Expand Down Expand Up @@ -2702,10 +2703,10 @@ bool SwingSchedulerDAG::canUseLastOffsetValue(MachineInstr *MI,
void SwingSchedulerDAG::applyInstrChange(MachineInstr *MI,
SMSchedule &Schedule) {
SUnit *SU = getSUnit(MI);
DenseMap<SUnit *, std::pair<unsigned, int64_t>>::iterator It =
DenseMap<SUnit *, std::pair<Register, int64_t>>::iterator It =
InstrChanges.find(SU);
if (It != InstrChanges.end()) {
std::pair<unsigned, int64_t> RegAndOffset = It->second;
std::pair<Register, int64_t> RegAndOffset = It->second;
unsigned BasePos, OffsetPos;
if (!TII->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
return;
Expand Down Expand Up @@ -2789,10 +2790,10 @@ bool SwingSchedulerDAG::mayOverlapInLaterIter(
if (!DefB || !DefO || !DefB->isPHI() || !DefO->isPHI())
return true;

unsigned InitValB = 0;
unsigned LoopValB = 0;
unsigned InitValO = 0;
unsigned LoopValO = 0;
Register InitValB;
Register LoopValB;
Register InitValO;
Register LoopValO;
getPhiRegs(*DefB, BB, InitValB, LoopValB);
getPhiRegs(*DefO, BB, InitValO, LoopValO);
MachineInstr *InitDefB = MRI.getVRegDef(InitValB);
Expand Down Expand Up @@ -3062,7 +3063,7 @@ void SMSchedule::orderDependence(const SwingSchedulerDAG *SSD, SUnit *SU,
unsigned BasePos, OffsetPos;
if (ST.getInstrInfo()->getBaseAndOffsetPosition(*MI, BasePos, OffsetPos))
if (MI->getOperand(BasePos).getReg() == Reg)
if (unsigned NewReg = SSD->getInstrBaseReg(SU))
if (Register NewReg = SSD->getInstrBaseReg(SU))
Reg = NewReg;
bool Reads, Writes;
std::tie(Reads, Writes) =
Expand Down Expand Up @@ -3180,8 +3181,8 @@ bool SMSchedule::isLoopCarried(const SwingSchedulerDAG *SSD,
unsigned DefCycle = cycleScheduled(DefSU);
int DefStage = stageScheduled(DefSU);

unsigned InitVal = 0;
unsigned LoopVal = 0;
Register InitVal;
Register LoopVal;
getPhiRegs(Phi, Phi.getParent(), InitVal, LoopVal);
SUnit *UseSU = SSD->getSUnit(MRI.getVRegDef(LoopVal));
if (!UseSU)
Expand Down Expand Up @@ -3212,7 +3213,7 @@ bool SMSchedule::isLoopCarriedDefOfUse(const SwingSchedulerDAG *SSD,
return false;
if (!isLoopCarried(SSD, *Phi))
return false;
unsigned LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
Register LoopReg = getLoopPhiReg(*Phi, Phi->getParent());
for (MachineOperand &DMO : Def->all_defs()) {
if (DMO.getReg() == LoopReg)
return true;
Expand Down Expand Up @@ -3434,8 +3435,8 @@ void SwingSchedulerDAG::checkValidNodeOrder(const NodeSetType &Circuits) const {
/// In this case p and p' overlap, which means that two registers are needed.
/// Instead, this function changes the load to use p' and updates the offset.
void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque<SUnit *> &Instrs) {
unsigned OverlapReg = 0;
unsigned NewBaseReg = 0;
Register OverlapReg;
Register NewBaseReg;
for (SUnit *SU : Instrs) {
MachineInstr *MI = SU->getInstr();
for (unsigned i = 0, e = MI->getNumOperands(); i < e; ++i) {
Expand All @@ -3445,8 +3446,8 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque<SUnit *> &Instrs) {
if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) {
// Check that the instruction appears in the InstrChanges structure,
// which contains instructions that can have the offset updated.
DenseMap<SUnit *, std::pair<unsigned, int64_t>>::iterator It =
InstrChanges.find(SU);
DenseMap<SUnit *, std::pair<Register, int64_t>>::iterator It =
InstrChanges.find(SU);
if (It != InstrChanges.end()) {
unsigned BasePos, OffsetPos;
// Update the base register and adjust the offset.
Expand All @@ -3461,8 +3462,8 @@ void SwingSchedulerDAG::fixupRegisterOverlaps(std::deque<SUnit *> &Instrs) {
NewMIs[MI] = NewMI;
}
}
OverlapReg = 0;
NewBaseReg = 0;
OverlapReg = Register();
NewBaseReg = Register();
break;
}
// Look for an instruction of the form p' = op(p), which uses and defines
Expand Down
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