[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM #130550

vikramRH · 2025-03-10T05:41:01Z

No description provided.

llvmbot · 2025-03-10T05:41:36Z

@llvm/pr-subscribers-backend-aarch64

@llvm/pr-subscribers-backend-amdgpu

Author: Vikram Hegde (vikramRH)

Changes

need to update few more tests..

Patch is 44.42 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130550.diff

35 Files Affected:

(added) llvm/include/llvm/CodeGen/PEI.h (+25)
(modified) llvm/include/llvm/InitializePasses.h (+1-1)
(modified) llvm/include/llvm/Passes/CodeGenPassBuilder.h (+1)
(modified) llvm/include/llvm/Passes/MachinePassRegistry.def (+1-1)
(modified) llvm/lib/CodeGen/CodeGen.cpp (+1-1)
(modified) llvm/lib/CodeGen/PrologEpilogInserter.cpp (+65-40)
(modified) llvm/lib/Passes/PassBuilder.cpp (+1)
(modified) llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir (+1)
(modified) llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir (+1)
(modified) llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir (+1)
(modified) llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir (+1)
(modified) llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir (+1)
(modified) llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir (+1)
(modified) llvm/test/CodeGen/AArch64/framelayout-sve.mir (+1)
(modified) llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir (+1)
(modified) llvm/test/CodeGen/AArch64/settag-merge.mir (+1)
(modified) llvm/test/CodeGen/AArch64/spill-stack-realignment.mir (+1)
(modified) llvm/test/CodeGen/AArch64/stack-id-pei-alloc.mir (+1)
(modified) llvm/test/CodeGen/AArch64/stack-probing-last-in-block.mir (+1)
(modified) llvm/test/CodeGen/AArch64/stack-tagging-epilogue-fold.mir (+1)
(modified) llvm/test/CodeGen/AArch64/stack-tagging-merge-past-memcpy.mir (+1)
(modified) llvm/test/CodeGen/AArch64/sve-ld1r.mir (+1)
(modified) llvm/test/CodeGen/AArch64/sve-ldN.mir (+1)
(modified) llvm/test/CodeGen/AArch64/sve-ldnf1.mir (+1)
(modified) llvm/test/CodeGen/AArch64/sve-ldstnt1.mir (+1)
(modified) llvm/test/CodeGen/AArch64/sve-stN.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/accvgpr-spill-scc-clobber.mir (+4)
(modified) llvm/test/CodeGen/AMDGPU/agpr-copy-reuse-writes.mir (+1)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-i32.mir (+8)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-add-u32.mir (+8)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-s-mov-b32.mir (+6)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-scalar-bit-ops.mir (+8)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32-wave32.mir (+2)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-co-u32.mir (+8)
(modified) llvm/test/CodeGen/AMDGPU/eliminate-frame-index-v-add-u32.mir (+6)

diff --git a/llvm/include/llvm/CodeGen/PEI.h b/llvm/include/llvm/CodeGen/PEI.h
new file mode 100644
index 0000000000000..750064ea64e87
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/PEI.h
@@ -0,0 +1,25 @@
+//===- llvm/CodeGen/PEI.h ---------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_PEI_H
+#define LLVM_CODEGEN_PEI_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class PrologEpilogInserterPass
+    : public PassInfoMixin<PrologEpilogInserterPass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_PEI_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index c2cb4cb4ef477..9ffd6f0054e4d 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -222,7 +222,7 @@ void initializeNaryReassociateLegacyPassPass(PassRegistry &);
 void initializeObjCARCContractLegacyPassPass(PassRegistry &);
 void initializeOptimizationRemarkEmitterWrapperPassPass(PassRegistry &);
 void initializeOptimizePHIsLegacyPass(PassRegistry &);
-void initializePEIPass(PassRegistry &);
+void initializePEILegacyPass(PassRegistry &);
 void initializePHIEliminationPass(PassRegistry &);
 void initializePartiallyInlineLibCallsLegacyPassPass(PassRegistry &);
 void initializePatchableFunctionPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 25899d04dc664..90310622742be 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -57,6 +57,7 @@
 #include "llvm/CodeGen/MachineSink.h"
 #include "llvm/CodeGen/MachineVerifier.h"
 #include "llvm/CodeGen/OptimizePHIs.h"
+#include "llvm/CodeGen/PEI.h"
 #include "llvm/CodeGen/PHIElimination.h"
 #include "llvm/CodeGen/PeepholeOptimizer.h"
 #include "llvm/CodeGen/PostRASchedulerList.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index f99a5f2c74bf3..dbc49f28c9d2a 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -173,6 +173,7 @@ MACHINE_FUNCTION_PASS("print<machine-post-dom-tree>",
                       MachinePostDominatorTreePrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(errs()))
 MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(errs()))
+MACHINE_FUNCTION_PASS("prolog-epilog", PrologEpilogInserterPass())
 MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
 MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
 MACHINE_FUNCTION_PASS("register-coalescer", RegisterCoalescerPass())
@@ -274,7 +275,6 @@ DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
 DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
 DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass)
 DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass)
-DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass)
 DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass)
 DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
 DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index beb7fb284a376..169c79248bd23 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -101,7 +101,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
   initializeMachineVerifierLegacyPassPass(Registry);
   initializeObjCARCContractLegacyPassPass(Registry);
   initializeOptimizePHIsLegacyPass(Registry);
-  initializePEIPass(Registry);
+  initializePEILegacyPass(Registry);
   initializePHIEliminationPass(Registry);
   initializePatchableFunctionPass(Registry);
   initializePeepholeOptimizerLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index 9b852c0fd49cf..913bfa576596b 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -36,6 +36,7 @@
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/PEI.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
@@ -77,21 +78,7 @@ STATISTIC(NumFuncSeen, "Number of functions seen in PEI");
 
 namespace {
 
-class PEI : public MachineFunctionPass {
-public:
-  static char ID;
-
-  PEI() : MachineFunctionPass(ID) {
-    initializePEIPass(*PassRegistry::getPassRegistry());
-  }
-
-  void getAnalysisUsage(AnalysisUsage &AU) const override;
-
-  /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
-  /// frame indexes with appropriate references.
-  bool runOnMachineFunction(MachineFunction &MF) override;
-
-private:
+class PEIImpl {
   RegScavenger *RS = nullptr;
 
   // MinCSFrameIndex, MaxCSFrameIndex - Keeps the range of callee saved
@@ -137,31 +124,50 @@ class PEI : public MachineFunctionPass {
 
   void insertPrologEpilogCode(MachineFunction &MF);
   void insertZeroCallUsedRegs(MachineFunction &MF);
+
+public:
+  PEIImpl(MachineOptimizationRemarkEmitter *ORE) : ORE(ORE) {}
+  bool run(MachineFunction &MF);
+};
+
+class PEILegacy : public MachineFunctionPass {
+public:
+  static char ID;
+
+  PEILegacy() : MachineFunctionPass(ID) {
+    initializePEILegacyPass(*PassRegistry::getPassRegistry());
+  }
+
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
+
+  /// runOnMachineFunction - Insert prolog/epilog code and replace abstract
+  /// frame indexes with appropriate references.
+  bool runOnMachineFunction(MachineFunction &MF) override;
 };
 
 } // end anonymous namespace
 
-char PEI::ID = 0;
+char PEILegacy::ID = 0;
 
-char &llvm::PrologEpilogCodeInserterID = PEI::ID;
+char &llvm::PrologEpilogCodeInserterID = PEILegacy::ID;
 
-INITIALIZE_PASS_BEGIN(PEI, DEBUG_TYPE, "Prologue/Epilogue Insertion", false,
-                      false)
+INITIALIZE_PASS_BEGIN(PEILegacy, DEBUG_TYPE, "Prologue/Epilogue Insertion",
+                      false, false)
 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
-INITIALIZE_PASS_END(PEI, DEBUG_TYPE,
+INITIALIZE_PASS_END(PEILegacy, DEBUG_TYPE,
                     "Prologue/Epilogue Insertion & Frame Finalization", false,
                     false)
 
 MachineFunctionPass *llvm::createPrologEpilogInserterPass() {
-  return new PEI();
+  return new PEILegacy();
 }
 
 STATISTIC(NumBytesStackSpace,
           "Number of bytes used for stack in all functions");
 
-void PEI::getAnalysisUsage(AnalysisUsage &AU) const {
+void PEILegacy::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.setPreservesCFG();
   AU.addPreserved<MachineLoopInfoWrapperPass>();
   AU.addPreserved<MachineDominatorTreeWrapperPass>();
@@ -213,9 +219,7 @@ static void stashEntryDbgValues(MachineBasicBlock &MBB,
       MI->removeFromParent();
 }
 
-/// runOnMachineFunction - Insert prolog/epilog code and replace abstract
-/// frame indexes with appropriate references.
-bool PEI::runOnMachineFunction(MachineFunction &MF) {
+bool PEIImpl::run(MachineFunction &MF) {
   NumFuncSeen++;
   const Function &F = MF.getFunction();
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
@@ -223,7 +227,6 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
 
   RS = TRI->requiresRegisterScavenging(MF) ? new RegScavenger() : nullptr;
   FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(MF);
-  ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
 
   // Spill frame pointer and/or base pointer registers if they are clobbered.
   // It is placed before call frame instruction elimination so it will not mess
@@ -354,9 +357,31 @@ bool PEI::runOnMachineFunction(MachineFunction &MF) {
   return true;
 }
 
+/// runOnMachineFunction - Insert prolog/epilog code and replace abstract
+/// frame indexes with appropriate references.
+bool PEILegacy::runOnMachineFunction(MachineFunction &MF) {
+  MachineOptimizationRemarkEmitter *ORE =
+      &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
+  return PEIImpl(ORE).run(MF);
+}
+
+PreservedAnalyses
+PrologEpilogInserterPass::run(MachineFunction &MF,
+                              MachineFunctionAnalysisManager &MFAM) {
+  MachineOptimizationRemarkEmitter &ORE =
+      MFAM.getResult<MachineOptimizationRemarkEmitterAnalysis>(MF);
+  if (!PEIImpl(&ORE).run(MF))
+    return PreservedAnalyses::all();
+
+  return getMachineFunctionPassPreservedAnalyses()
+      .preserveSet<CFGAnalyses>()
+      .preserve<MachineDominatorTreeAnalysis>()
+      .preserve<MachineLoopAnalysis>();
+}
+
 /// Calculate the MaxCallFrameSize variable for the function's frame
 /// information and eliminate call frame pseudo instructions.
-void PEI::calculateCallFrameInfo(MachineFunction &MF) {
+void PEIImpl::calculateCallFrameInfo(MachineFunction &MF) {
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
   MachineFrameInfo &MFI = MF.getFrameInfo();
@@ -397,7 +422,7 @@ void PEI::calculateCallFrameInfo(MachineFunction &MF) {
 
 /// Compute the sets of entry and return blocks for saving and restoring
 /// callee-saved registers, and placing prolog and epilog code.
-void PEI::calculateSaveRestoreBlocks(MachineFunction &MF) {
+void PEIImpl::calculateSaveRestoreBlocks(MachineFunction &MF) {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
 
   // Even when we do not change any CSR, we still want to insert the
@@ -651,7 +676,7 @@ static void insertCSRRestores(MachineBasicBlock &RestoreBlock,
   }
 }
 
-void PEI::spillCalleeSavedRegs(MachineFunction &MF) {
+void PEIImpl::spillCalleeSavedRegs(MachineFunction &MF) {
   // We can't list this requirement in getRequiredProperties because some
   // targets (WebAssembly) use virtual registers past this point, and the pass
   // pipeline is set up without giving the passes a chance to look at the
@@ -843,7 +868,7 @@ static void AssignProtectedObjSet(const StackObjSet &UnassignedObjs,
 
 /// calculateFrameObjectOffsets - Calculate actual frame offsets for all of the
 /// abstract stack objects.
-void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
+void PEIImpl::calculateFrameObjectOffsets(MachineFunction &MF) {
   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
 
   bool StackGrowsDown =
@@ -1158,7 +1183,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &MF) {
 /// insertPrologEpilogCode - Scan the function for modified callee saved
 /// registers, insert spill code for these callee saved registers, then add
 /// prolog and epilog code to the function.
-void PEI::insertPrologEpilogCode(MachineFunction &MF) {
+void PEIImpl::insertPrologEpilogCode(MachineFunction &MF) {
   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
 
   // Add prologue to the function...
@@ -1195,7 +1220,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &MF) {
 }
 
 /// insertZeroCallUsedRegs - Zero out call used registers.
-void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
+void PEIImpl::insertZeroCallUsedRegs(MachineFunction &MF) {
   const Function &F = MF.getFunction();
 
   if (!F.hasFnAttribute("zero-call-used-regs"))
@@ -1338,7 +1363,7 @@ void PEI::insertZeroCallUsedRegs(MachineFunction &MF) {
 
 /// Replace all FrameIndex operands with physical register references and actual
 /// offsets.
-void PEI::replaceFrameIndicesBackward(MachineFunction &MF) {
+void PEIImpl::replaceFrameIndicesBackward(MachineFunction &MF) {
   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
 
   for (auto &MBB : MF) {
@@ -1366,7 +1391,7 @@ void PEI::replaceFrameIndicesBackward(MachineFunction &MF) {
 
 /// replaceFrameIndices - Replace all MO_FrameIndex operands with physical
 /// register references and actual offsets.
-void PEI::replaceFrameIndices(MachineFunction &MF) {
+void PEIImpl::replaceFrameIndices(MachineFunction &MF) {
   const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
 
   for (auto &MBB : MF) {
@@ -1382,8 +1407,8 @@ void PEI::replaceFrameIndices(MachineFunction &MF) {
   }
 }
 
-bool PEI::replaceFrameIndexDebugInstr(MachineFunction &MF, MachineInstr &MI,
-                                      unsigned OpIdx, int SPAdj) {
+bool PEIImpl::replaceFrameIndexDebugInstr(MachineFunction &MF, MachineInstr &MI,
+                                          unsigned OpIdx, int SPAdj) {
   const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
   if (MI.isDebugValue()) {
@@ -1464,8 +1489,8 @@ bool PEI::replaceFrameIndexDebugInstr(MachineFunction &MF, MachineInstr &MI,
   return false;
 }
 
-void PEI::replaceFrameIndicesBackward(MachineBasicBlock *BB,
-                                      MachineFunction &MF, int &SPAdj) {
+void PEIImpl::replaceFrameIndicesBackward(MachineBasicBlock *BB,
+                                          MachineFunction &MF, int &SPAdj) {
   assert(MF.getSubtarget().getRegisterInfo() &&
          "getRegisterInfo() must be implemented!");
 
@@ -1509,8 +1534,8 @@ void PEI::replaceFrameIndicesBackward(MachineBasicBlock *BB,
   }
 }
 
-void PEI::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
-                              int &SPAdj) {
+void PEIImpl::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
+                                  int &SPAdj) {
   assert(MF.getSubtarget().getRegisterInfo() &&
          "getRegisterInfo() must be implemented!");
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 8080059f0bb03..4b5b4af298e84 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -128,6 +128,7 @@
 #include "llvm/CodeGen/MachineTraceMetrics.h"
 #include "llvm/CodeGen/MachineVerifier.h"
 #include "llvm/CodeGen/OptimizePHIs.h"
+#include "llvm/CodeGen/PEI.h"
 #include "llvm/CodeGen/PHIElimination.h"
 #include "llvm/CodeGen/PeepholeOptimizer.h"
 #include "llvm/CodeGen/PostRASchedulerList.h"
diff --git a/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir b/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
index f920813f2b42d..434a0e3c82a1d 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-large-stack-spbump.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64 -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -passes='prolog-epilog' %s -o - | FileCheck %s
 --- |
   define i32 @_Z4funcv() {
   entry:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir b/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
index 15b8e759dec42..af0345d9fc3e7 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
+++ b/llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-linux-gnu -passes='prolog-epilog' %s -o - | FileCheck %s
 
 # The tests below test the allocation of 128bit callee-saves
 # on the stack, specifically their offsets.
diff --git a/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir b/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
index 59b04dd5052fd..7b9d9670a68a6 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-offset-immediate-change.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='prolog-epilog' %s -o - | FileCheck %s
 ---
 name: framelayout_offset_immediate_change
 tracksRegLiveness: true
diff --git a/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir b/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
index 390582969d026..6ee499247e09c 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-scavengingslot.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='prolog-epilog'  %s -o - | FileCheck %s
 ---
 # This test verifies that the emergency scavenging slot is located near
 # the SP when the stack is realigned.
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
index 26b7ca3bf8c07..3cb1a13dadbc4 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='prolog-epilog' %s -o - | FileCheck %s
 --- |
     define void @hasBasepointer() #0 { ret void }
     define void @hasBasepointer_sme_streaming() #1 { ret void }
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir b/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
index 680f9c335c250..3cef527d38f81 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve-scavengingslot.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog -mattr=+sve %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64-none-linux-gnu -passes='prolog-epilog' -mattr=+sve %s -o - | FileCheck %s
 ---
 # This test verifies that the emergency scavenging slot is located near the SP/BP.
 name: LateScavengingSlot
diff --git a/llvm/test/CodeGen/AArch64/framelayout-sve.mir b/llvm/test/CodeGen/AArch64/framelayout-sve.mir
index 17b1ad2197c46..b1ad4893fdc4f 100644
--- a/llvm/test/CodeGen/AArch64/framelayout-sve.mir
+++ b/llvm/test/CodeGen/AArch64/framelayout-sve.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -passes='prolog-epilog' %s -o - | FileCheck %s
 # RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -start-before=prologepilog %s -o - | FileCheck %s --check-prefix=ASM
 # RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+sve -start-before=prologepilog %s -filetype=obj -o %t
 # RUN: llvm-objdump --dwarf=frames %t | FileCheck %s --check-prefix=UNWINDINFO
diff --git a/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir b/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
index 3db69cfb21593..e1bb6d1fad17c 100644
--- a/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
+++ b/llvm/test/CodeGen/AArch64/reg-scavenge-frame.mir
@@ -1,4 +1,5 @@
 # RUN: llc -run-pass=prologepilog -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -passes='prolog-epilog' %s -o - | FileCheck %s
 
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
diff --git a/llvm/test/CodeGen/AArch64/settag-merge.mir b/llvm/test/CodeGen/AArch64/settag-merge.mir
index 1eb23ef9cba75..09da9ac4c1b82 100644
--- a/llvm/test/CodeGen/AArch64/settag-merge.mir
+++ b/llvm/test/CodeGen/AArch64/settag-merge.mir
@@ -1,4 +1,5 @@
 # RUN: llc -mtriple=aarch64 -mattr=+mte -run-pass=prologepilog %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -mattr=+mte -passes='prolog-epilog' %s -o - | FileCheck %s
 
 --- |
   declare void @llvm.aarch64.settag(ptr nocapture writeonly, i64) argmemonly nounwind writeonly "target-features"="+mte"
diff --git a/llvm/test/CodeGen/AArch64/spill-stack-realignment.mir b/llvm/test/CodeGen/AArch64/spill-...
[truncated]

llvm/test/CodeGen/AArch64/framelayout-sve-basepointer.mir

llvm/include/llvm/CodeGen/PEI.h

vikramRH requested review from arsenm, paperchalice, cdevadas and optimisan March 10, 2025 05:41

llvmbot added backend:AArch64 backend:AMDGPU labels Mar 10, 2025

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[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM

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vikramRH force-pushed the pei_npm branch from 9b67ac6 to 3f6ac9e Compare March 10, 2025 05:57

arsenm approved these changes Mar 10, 2025

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arsenm added the llvm:codegen label Mar 10, 2025

fix test case

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vikramRH added 2 commits April 15, 2025 13:35

Merge branch 'main' into pei_npm

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Merge branch 'main' into pei_npm

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arsenm approved these changes Apr 29, 2025

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vikramRH merged commit 86d8e8d into llvm:main Apr 29, 2025
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gizmondo pushed a commit to gizmondo/llvm-project that referenced this pull request Apr 29, 2025

[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (llvm#130550)

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IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (llvm#130550)

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IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (llvm#130550)

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IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (llvm#130550)

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GeorgeARM pushed a commit to GeorgeARM/llvm-project that referenced this pull request May 7, 2025

[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (llvm#130550)

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Ankur-0429 pushed a commit to Ankur-0429/llvm-project that referenced this pull request May 9, 2025

[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM (llvm#130550)

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[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM #130550

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[CodeGen][NewPM] Port "PrologEpilogInserter" to NPM #130550

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