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[MIPS] Add MIPS i6400 and i6500 processors #130587

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Merged
merged 5 commits into from
Mar 21, 2025
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Merged

[MIPS] Add MIPS i6400 and i6500 processors #130587

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4f9c5b5
[MIPS] Add MIPS i6400 and i6500 processors
mgoudar Mar 10, 2025
73338e1
[MIPS] Add comments to MipsSubTarget.h changes
mgoudar Mar 10, 2025
97e5e91
[MIPS] Use single SubTargetFeature for both i6400 and i6500
mgoudar Mar 12, 2025
e7442a7
[MIPS] Update comments in Mips.td
mgoudar Mar 12, 2025
9c8ca52
[MIPS] Add test to validate abi for --target mips64-gnu-linux
mgoudar Mar 19, 2025
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4 changes: 3 additions & 1 deletion clang/lib/Basic/Targets/Mips.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -47,14 +47,16 @@ bool MipsTargetInfo::processorSupportsGPR64() const {
.Case("mips64r6", true)
.Case("octeon", true)
.Case("octeon+", true)
.Case("i6400", true)
.Case("i6500", true)
.Default(false);
}

static constexpr llvm::StringLiteral ValidCPUNames[] = {
{"mips1"}, {"mips2"}, {"mips3"}, {"mips4"}, {"mips5"},
{"mips32"}, {"mips32r2"}, {"mips32r3"}, {"mips32r5"}, {"mips32r6"},
{"mips64"}, {"mips64r2"}, {"mips64r3"}, {"mips64r5"}, {"mips64r6"},
{"octeon"}, {"octeon+"}, {"p5600"}};
{"octeon"}, {"octeon+"}, {"p5600"}, {"i6400"}, {"i6500"}};

bool MipsTargetInfo::isValidCPUName(StringRef Name) const {
return llvm::is_contained(ValidCPUNames, Name);
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4 changes: 4 additions & 0 deletions clang/lib/Driver/ToolChains/Arch/Mips.cpp
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Expand Up @@ -104,6 +104,8 @@ void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple,
.Case("mips64r6", "n64")
.Case("octeon", "n64")
.Case("p5600", "o32")
.Case("i6400", "n64")
.Case("i6500", "n64")
.Default("");
}

Expand Down Expand Up @@ -514,5 +516,7 @@ bool mips::supportsIndirectJumpHazardBarrier(StringRef &CPU) {
.Case("mips64r6", true)
.Case("octeon", true)
.Case("p5600", true)
.Case("i6400", true)
.Case("i6500", true)
.Default(false);
}
4 changes: 3 additions & 1 deletion clang/lib/Driver/ToolChains/Gnu.cpp
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Expand Up @@ -1501,7 +1501,9 @@ bool clang::driver::findMIPSMultilibs(const Driver &D,
CPUName == "mips64r5" || CPUName == "octeon" ||
CPUName == "octeon+",
"-march=mips64r2", Flags);
addMultilibFlag(CPUName == "mips64r6", "-march=mips64r6", Flags);
addMultilibFlag(CPUName == "mips64r6" || CPUName == "i6400" ||
CPUName == "i6500",
"-march=mips64r6", Flags);
addMultilibFlag(isMicroMips(Args), "-mmicromips", Flags);
addMultilibFlag(tools::mips::isUCLibc(Args), "-muclibc", Flags);
addMultilibFlag(tools::mips::isNaN2008(D, Args, TargetTriple), "-mnan=2008",
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48 changes: 48 additions & 0 deletions clang/test/Driver/mips-abi.c
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Expand Up @@ -121,6 +121,54 @@
// MIPS-ARCH-P5600-N64: error: ABI 'n64' is not supported on CPU 'p5600'
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
// RUN: -march=i6400 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS-ARCH-I6400 %s
// MIPS-ARCH-I6400: "-target-cpu" "i6400"
// MIPS-ARCH-I6400: "-target-abi" "o32"
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
// RUN: -march=i6400 -mabi=64 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS-ARCH-I6400-N64 %s
// MIPS-ARCH-I6400-N64: "-target-cpu" "i6400"
// MIPS-ARCH-I6400-N64: "-target-abi" "n64"
//
// RUN: %clang --target=mips64-linux-gnu -### -c %s \
// RUN: -march=i6400 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-ARCH-I6400 %s
// MIPS64-ARCH-I6400: "-target-cpu" "i6400"
// MIPS64-ARCH-I6400: "-target-abi" "n64"
//
// RUN: %clang --target=mips64-linux-gnu -### -c %s \
// RUN: -march=i6400 -mabi=32 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-ARCH-I6400-O32 %s
// MIPS64-ARCH-I6400-O32: "-target-cpu" "i6400"
// MIPS64-ARCH-I6400-O32: "-target-abi" "o32"
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
// RUN: -march=i6500 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS-ARCH-I6500 %s
// MIPS-ARCH-I6500: "-target-cpu" "i6500"
// MIPS-ARCH-I6500: "-target-abi" "o32"
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
// RUN: -march=i6500 -mabi=64 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS-ARCH-I6500-N64 %s
// MIPS-ARCH-I6500-N64: "-target-cpu" "i6500"
// MIPS-ARCH-I6500-N64: "-target-abi" "n64"
//
// RUN: %clang --target=mips64-linux-gnu -### -c %s \
// RUN: -march=i6500 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-ARCH-I6500 %s
// MIPS64-ARCH-I6500: "-target-cpu" "i6500"
// MIPS64-ARCH-I6500: "-target-abi" "n64"
//
// RUN: %clang --target=mips64-linux-gnu -### -c %s \
// RUN: -march=i6500 -mabi=32 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS64-ARCH-I6500-O32 %s
// MIPS64-ARCH-I6500-O32: "-target-cpu" "i6500"
// MIPS54-ARCH-I6500-O32: "-target-abi" "o32"
//
// RUN: %clang --target=mips-linux-gnu -### -c %s \
// RUN: -march=mips64 2>&1 \
// RUN: | FileCheck -check-prefix=MIPS-ARCH-3264 %s
// MIPS-ARCH-3264: "-target-cpu" "mips64"
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2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -101,6 +101,8 @@ Changes to the LoongArch Backend
Changes to the MIPS Backend
---------------------------

* `-mcpu=i6400` and `-mcpu=i6500` were added.

Changes to the PowerPC Backend
------------------------------

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8 changes: 8 additions & 0 deletions llvm/lib/Target/Mips/Mips.td
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Expand Up @@ -238,6 +238,12 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
"MipsSubtarget::CPU::P5600",
"The P5600 Processor", [FeatureMips32r5]>;

// The I6500 is the multi-cluster version of the I6400. Both are based on the
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
"MIPS I6400/I6500 Processors", [FeatureMips64r6]>;

class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;

Expand All @@ -261,6 +267,8 @@ def : Proc<"mips64r6", [FeatureMips64r6]>;
def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
def : ProcessorModel<"i6500", NoSchedModel, [ImplI6400]>;

def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/Mips/MipsSubtarget.h
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Expand Up @@ -43,7 +43,7 @@ class MipsSubtarget : public MipsGenSubtargetInfo {
Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
};

enum class CPU { P5600 };
enum class CPU { P5600, I6400 };
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do we need "i6500" here as well?

i6500 is just a multi-cluster version of i6400, right?

Please also attach/link documentation files for those CPUs.

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@mgoudar mgoudar Mar 10, 2025 •
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Thanks for quick review!
yes. i6500 is multi-cluster version of i6400 and both are based on MIPS64 Release 6 ISA.
Hence I kept single subtarget I6400 and reused it in Mips.td for both i6400 and i6500.
I have added comments in the changed file MipsSubTarget.h

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So, we do not use this in this patch at all, right? If that is the case, please leave this change for the Sched. Model PR.

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Hi, we need this change in Mips.td as we are defining 2 new cpu (i6400 and i6500) with NoSchedModel.
In the third commit, I have defined single SubTargetFeature and reused it for both i6400 and i6500 as both are based on same CPU.
Please review.


// Used to avoid printing dsp warnings multiple times.
static bool DspWarningPrinted;
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