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AMDGPU: Replace insertelement poison with insertelement undef #130896

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Mar 12, 2025
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AMDGPU: Replace insertelement poison with insertelement undef #130896

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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
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Expand Up @@ -266,7 +266,7 @@ define <4 x float> @v_uitofp_unpack_i32_to_v4f32(i32 %arg0) nounwind {
%mask.lshr.24 = and i32 %lshr.24, 255
%cvt3 = uitofp i32 %mask.lshr.24 to float

%ins.0 = insertelement <4 x float> undef, float %cvt0, i32 0
%ins.0 = insertelement <4 x float> poison, float %cvt0, i32 0
%ins.1 = insertelement <4 x float> %ins.0, float %cvt1, i32 1
%ins.2 = insertelement <4 x float> %ins.1, float %cvt2, i32 2
%ins.3 = insertelement <4 x float> %ins.2, float %cvt3, i32 3
Expand Down
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
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Expand Up @@ -1061,7 +1061,6 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
Expand All @@ -1081,7 +1080,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
%load2 = load volatile i32, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef

%insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
%insert.0 = insertelement <3 x i32> poison, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
Expand All @@ -1097,7 +1096,6 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
Expand All @@ -1117,7 +1115,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
%load2 = load volatile float, ptr addrspace(3) undef
%load3 = load volatile i32, ptr addrspace(3) undef

%insert.0 = insertelement <3 x float> undef, float %load0, i32 0
%insert.0 = insertelement <3 x float> poison, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
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Expand Up @@ -17,7 +17,7 @@ bb:
%load = load <2 x i32>, ptr addrspace(3) %gep, align 4
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
%v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr addrspace(3) %gep, align 4
ret void
Expand All @@ -39,7 +39,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
Expand All @@ -62,7 +62,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
%v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr addrspace(3) %gep, align 4
Expand All @@ -79,7 +79,7 @@ bb:
%load = load <2 x i32>, ptr addrspace(3) %gep, align 8
%v1 = extractelement <2 x i32> %load, i32 0
%v2 = extractelement <2 x i32> %load, i32 1
%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
%v3 = insertelement <2 x i32> poison, i32 %v2, i32 0
%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
store <2 x i32> %v4, ptr addrspace(3) %gep, align 8
ret void
Expand All @@ -96,7 +96,7 @@ bb:
%v1 = extractelement <3 x i32> %load, i32 0
%v2 = extractelement <3 x i32> %load, i32 1
%v3 = extractelement <3 x i32> %load, i32 2
%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
%v5 = insertelement <3 x i32> poison, i32 %v3, i32 0
%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
store <3 x i32> %v7, ptr addrspace(3) %gep, align 16
Expand All @@ -121,7 +121,7 @@ bb:
%v2 = extractelement <4 x i32> %load, i32 1
%v3 = extractelement <4 x i32> %load, i32 2
%v4 = extractelement <4 x i32> %load, i32 3
%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
%v5 = insertelement <4 x i32> poison, i32 %v4, i32 0
%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
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Expand Up @@ -33,13 +33,13 @@ define amdgpu_ps <4 x float> @image_bvh_intersect_ray_flat(i32 %node_ptr, float
; GCN-NEXT: image_bvh_intersect_ray v[0:3], v[0:10], s[0:3]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
%ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
%ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
%ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
%ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
%ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
%ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
Expand Down Expand Up @@ -96,13 +96,13 @@ define amdgpu_ps <4 x float> @image_bvh64_intersect_ray_flat(<2 x i32> %node_ptr
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ; return to shader part epilog
%node_ptr = bitcast <2 x i32> %node_ptr_vec to i64
%ray_origin0 = insertelement <3 x float> undef, float %ray_origin_x, i32 0
%ray_origin0 = insertelement <3 x float> poison, float %ray_origin_x, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float %ray_origin_y, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float %ray_origin_z, i32 2
%ray_dir0 = insertelement <3 x float> undef, float %ray_dir_x, i32 0
%ray_dir0 = insertelement <3 x float> poison, float %ray_dir_x, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float %ray_dir_y, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float %ray_dir_z, i32 2
%ray_inv_dir0 = insertelement <3 x float> undef, float %ray_inv_dir_x, i32 0
%ray_inv_dir0 = insertelement <3 x float> poison, float %ray_inv_dir_x, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float %ray_inv_dir_y, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float %ray_inv_dir_z, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
Expand Down Expand Up @@ -725,13 +725,13 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
%node_ptr = load i32, ptr %gep_node_ptr, align 4
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
%ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
%ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
%ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
%ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
Expand Down Expand Up @@ -829,13 +829,13 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
%node_ptr = load i32, ptr %gep_node_ptr, align 4
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
%ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
%ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
%ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
%ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
Expand Down Expand Up @@ -911,13 +911,13 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
%ray_dir0 = insertelement <3 x float> undef, float 3.0, i32 0
%ray_dir0 = insertelement <3 x float> poison, float 3.0, i32 0
%ray_dir1 = insertelement <3 x float> %ray_dir0, float 4.0, i32 1
%ray_dir = insertelement <3 x float> %ray_dir1, float 5.0, i32 2
%ray_inv_dir0 = insertelement <3 x float> undef, float 6.0, i32 0
%ray_inv_dir0 = insertelement <3 x float> poison, float 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
Expand Down Expand Up @@ -985,13 +985,13 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
%gep_ray = getelementptr inbounds float, ptr %p_ray, i32 %lid
%ray_extent = load float, ptr %gep_ray, align 4
%ray_origin0 = insertelement <3 x float> undef, float 0.0, i32 0
%ray_origin0 = insertelement <3 x float> poison, float 0.0, i32 0
%ray_origin1 = insertelement <3 x float> %ray_origin0, float 1.0, i32 1
%ray_origin = insertelement <3 x float> %ray_origin1, float 2.0, i32 2
%ray_dir0 = insertelement <3 x half> undef, half 3.0, i32 0
%ray_dir0 = insertelement <3 x half> poison, half 3.0, i32 0
%ray_dir1 = insertelement <3 x half> %ray_dir0, half 4.0, i32 1
%ray_dir = insertelement <3 x half> %ray_dir1, half 5.0, i32 2
%ray_inv_dir0 = insertelement <3 x half> undef, half 6.0, i32 0
%ray_inv_dir0 = insertelement <3 x half> poison, half 6.0, i32 0
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
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Expand Up @@ -368,7 +368,7 @@ define amdgpu_ps i64 @s_sdiv_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
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Expand Up @@ -358,7 +358,7 @@ define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
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Expand Up @@ -355,7 +355,7 @@ define amdgpu_ps i64 @s_udiv_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
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Expand Up @@ -349,7 +349,7 @@ define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
%elt.1 = extractelement <2 x i32> %cast, i32 1
%res.0 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.0)
%res.1 = call i32 @llvm.amdgcn.readfirstlane(i32 %elt.1)
%ins.0 = insertelement <2 x i32> undef, i32 %res.0, i32 0
%ins.0 = insertelement <2 x i32> poison, i32 %res.0, i32 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %res.0, i32 1
%cast.back = bitcast <2 x i32> %ins.1 to i64
ret i64 %cast.back
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll
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Expand Up @@ -90,7 +90,7 @@ entry:
%xor = xor i32 %a, %b
%r0.val = xor i32 %xor, -1
%r1.val = add i32 %xor, %a
%ins0 = insertelement <2 x i32> undef, i32 %r0.val, i32 0
%ins0 = insertelement <2 x i32> poison, i32 %r0.val, i32 0
%ins1 = insertelement <2 x i32> %ins0, i32 %r1.val, i32 1
ret <2 x i32> %ins1
}
Expand Down Expand Up @@ -196,7 +196,7 @@ define amdgpu_ps <2 x i64> @scalar_xnor_i64_mul_use(i64 inreg %a, i64 inreg %b)
%xor = xor i64 %a, %b
%r0.val = xor i64 %xor, -1
%r1.val = add i64 %xor, %a
%ins0 = insertelement <2 x i64> undef, i64 %r0.val, i32 0
%ins0 = insertelement <2 x i64> poison, i64 %r0.val, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 %r1.val, i32 1
ret <2 x i64> %ins1
}
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/add3.ll
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Expand Up @@ -181,7 +181,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%x1 = mul i32 %outer, %x
%r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
%r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
Expand All @@ -207,7 +207,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
%r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
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Expand Up @@ -17,7 +17,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre

.beginls: ; preds = %.entry
%tmp15 = extractelement <6 x i32> %arg8, i32 3
%.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
%.0.vec.insert.i = insertelement <2 x i32> poison, i32 %tmp15, i32 0
%.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
%tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
br label %.endls
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
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Expand Up @@ -36,7 +36,7 @@ bb:
%tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
%tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
%tmp24 = extractelement <16 x i8> %tmp23, i64 3
%tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
%tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
%tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
%tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
%tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/anyext.ll
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Expand Up @@ -187,7 +187,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
; GFX9-NEXT: s_endpgm
bb:
%tmp = load i16, ptr addrspace(1) undef, align 2
%tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
%tmp2 = insertelement <2 x i16> poison, i16 %tmp, i32 1
%tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
%tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
%tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
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Expand Up @@ -189,7 +189,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
entry:
%a.cvt = fptrunc float %a to bfloat
%b.cvt = fptrunc float %b to bfloat
%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
Expand Down Expand Up @@ -226,7 +226,7 @@ entry:
%a.cvt = fptrunc float %a.neg to bfloat
%b.abs = call float @llvm.fabs.f32(float %b)
%b.cvt = fptrunc float %b.abs to bfloat
%v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
%v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AMDGPU/bfi_nested.ll
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Expand Up @@ -297,7 +297,7 @@ define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %o
; GCN-NEXT: s_endpgm
%shift = lshr i32 %b, 16
%tr = trunc i32 %shift to i16
%tmp = insertelement <2 x i16> undef, i16 %a, i32 0
%tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
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