AMDGPU: Replace insertelement poison with insertelement undef #130896
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis is the bulk update with perl, with cases which require additional Patch is 300.54 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/130896.diff 136 Files Affected:
diff --git a/llvm/test/CodeGen/AMDGPU/add3.ll b/llvm/test/CodeGen/AMDGPU/add3.ll
index d3f9c2d0fbc54..0d80296bb67b6 100644
--- a/llvm/test/CodeGen/AMDGPU/add3.ll
+++ b/llvm/test/CodeGen/AMDGPU/add3.ll
@@ -181,7 +181,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
%x1 = mul i32 %outer, %x
- %r1 = insertelement <2 x i32> undef, i32 %outer, i32 0
+ %r1 = insertelement <2 x i32> poison, i32 %outer, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
@@ -207,7 +207,7 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {
; GFX10-NEXT: ; return to shader part epilog
%inner = add i32 %a, %b
%outer = add i32 %inner, %c
- %r1 = insertelement <2 x i32> undef, i32 %inner, i32 0
+ %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0
%r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1
%bc = bitcast <2 x i32> %r0 to <2 x float>
ret <2 x float> %bc
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll b/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
index 2aea4497c12ba..b610fca02f92e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll
@@ -17,7 +17,7 @@ define amdgpu_hs void @_amdgpu_hs_main(i32 inreg %arg, i32 inreg %arg1, i32 inre
.beginls: ; preds = %.entry
%tmp15 = extractelement <6 x i32> %arg8, i32 3
- %.0.vec.insert.i = insertelement <2 x i32> undef, i32 %tmp15, i32 0
+ %.0.vec.insert.i = insertelement <2 x i32> poison, i32 %tmp15, i32 0
%.4.vec.insert.i = shufflevector <2 x i32> %.0.vec.insert.i, <2 x i32> undef, <2 x i32> <i32 0, i32 3>
%tmp16 = bitcast <2 x i32> %.4.vec.insert.i to i64
br label %.endls
diff --git a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
index 07e39d798f58d..8bcef24c8e23d 100644
--- a/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll
@@ -36,7 +36,7 @@ bb:
%tmp21 = getelementptr inbounds <8 x i8>, ptr addrspace(1) %arg, i64 4
%tmp23 = load <16 x i8>, ptr addrspace(1) %tmp21, align 16
%tmp24 = extractelement <16 x i8> %tmp23, i64 3
- %tmp1 = insertelement <16 x i8> undef, i8 %tmp3, i32 2
+ %tmp1 = insertelement <16 x i8> poison, i8 %tmp3, i32 2
%tmp4 = insertelement <16 x i8> %tmp1, i8 0, i32 3
%tmp5 = insertelement <16 x i8> %tmp4, i8 0, i32 4
%tmp7 = insertelement <16 x i8> %tmp5, i8 %tmp6, i32 5
diff --git a/llvm/test/CodeGen/AMDGPU/anyext.ll b/llvm/test/CodeGen/AMDGPU/anyext.ll
index 6e16c90033273..f0aa141e65a5c 100644
--- a/llvm/test/CodeGen/AMDGPU/anyext.ll
+++ b/llvm/test/CodeGen/AMDGPU/anyext.ll
@@ -187,7 +187,7 @@ define amdgpu_kernel void @anyext_v2i16_to_v2i32() #0 {
; GFX9-NEXT: s_endpgm
bb:
%tmp = load i16, ptr addrspace(1) undef, align 2
- %tmp2 = insertelement <2 x i16> undef, i16 %tmp, i32 1
+ %tmp2 = insertelement <2 x i16> poison, i16 %tmp, i32 1
%tmp4 = and <2 x i16> %tmp2, <i16 -32767, i16 -32767>
%tmp5 = zext <2 x i16> %tmp4 to <2 x i32>
%tmp6 = shl nuw <2 x i32> %tmp5, <i32 16, i32 16>
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
index 0b5d47df2cc35..4c01e583713a7 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-conversions.ll
@@ -189,7 +189,7 @@ define amdgpu_ps float @fptrunc_f32_f32_to_v2bf16(float %a, float %b) {
entry:
%a.cvt = fptrunc float %a to bfloat
%b.cvt = fptrunc float %b to bfloat
- %v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
+ %v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
@@ -226,7 +226,7 @@ entry:
%a.cvt = fptrunc float %a.neg to bfloat
%b.abs = call float @llvm.fabs.f32(float %b)
%b.cvt = fptrunc float %b.abs to bfloat
- %v2.1 = insertelement <2 x bfloat> undef, bfloat %a.cvt, i32 0
+ %v2.1 = insertelement <2 x bfloat> poison, bfloat %a.cvt, i32 0
%v2.2 = insertelement <2 x bfloat> %v2.1, bfloat %b.cvt, i32 1
%ret = bitcast <2 x bfloat> %v2.2 to float
ret float %ret
diff --git a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
index 4b38215ebc597..3d52c158a6017 100644
--- a/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
+++ b/llvm/test/CodeGen/AMDGPU/bfi_nested.ll
@@ -297,7 +297,7 @@ define amdgpu_kernel void @v_bfi_dont_applied_for_scalar_ops(ptr addrspace(1) %o
; GCN-NEXT: s_endpgm
%shift = lshr i32 %b, 16
%tr = trunc i32 %shift to i16
- %tmp = insertelement <2 x i16> undef, i16 %a, i32 0
+ %tmp = insertelement <2 x i16> poison, i16 %a, i32 0
%vec = insertelement <2 x i16> %tmp, i16 %tr, i32 1
%val = bitcast <2 x i16> %vec to i32
store i32 %val, ptr addrspace(1) %out, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/big_alu.ll b/llvm/test/CodeGen/AMDGPU/big_alu.ll
index 0daa14a63f21a..b3b6259838341 100644
--- a/llvm/test/CodeGen/AMDGPU/big_alu.ll
+++ b/llvm/test/CodeGen/AMDGPU/big_alu.ll
@@ -90,11 +90,11 @@ main_body:
br i1 %tmp81, label %IF137, label %ENDIF136
IF137: ; preds = %main_body
- %tmp82 = insertelement <4 x float> undef, float %tmp30, i32 0
+ %tmp82 = insertelement <4 x float> poison, float %tmp30, i32 0
%tmp83 = insertelement <4 x float> %tmp82, float %tmp31, i32 1
%tmp84 = insertelement <4 x float> %tmp83, float %tmp32, i32 2
%tmp85 = insertelement <4 x float> %tmp84, float 0.000000e+00, i32 3
- %tmp86 = insertelement <4 x float> undef, float %tmp30, i32 0
+ %tmp86 = insertelement <4 x float> poison, float %tmp30, i32 0
%tmp87 = insertelement <4 x float> %tmp86, float %tmp31, i32 1
%tmp88 = insertelement <4 x float> %tmp87, float %tmp32, i32 2
%tmp89 = insertelement <4 x float> %tmp88, float 0.000000e+00, i32 3
@@ -103,20 +103,20 @@ IF137: ; preds = %main_body
%tmp92 = fmul float %tmp30, %tmp91
%tmp93 = fmul float %tmp31, %tmp91
%tmp94 = fmul float %tmp32, %tmp91
- %tmp95 = insertelement <4 x float> undef, float %tmp92, i32 0
+ %tmp95 = insertelement <4 x float> poison, float %tmp92, i32 0
%tmp96 = insertelement <4 x float> %tmp95, float %tmp93, i32 1
%tmp97 = insertelement <4 x float> %tmp96, float %tmp94, i32 2
%tmp98 = insertelement <4 x float> %tmp97, float 0.000000e+00, i32 3
- %tmp99 = insertelement <4 x float> undef, float %tmp37, i32 0
+ %tmp99 = insertelement <4 x float> poison, float %tmp37, i32 0
%tmp100 = insertelement <4 x float> %tmp99, float %tmp38, i32 1
%tmp101 = insertelement <4 x float> %tmp100, float %tmp39, i32 2
%tmp102 = insertelement <4 x float> %tmp101, float 0.000000e+00, i32 3
%tmp103 = call float @llvm.r600.dot4(<4 x float> %tmp98, <4 x float> %tmp102)
- %tmp104 = insertelement <4 x float> undef, float %tmp92, i32 0
+ %tmp104 = insertelement <4 x float> poison, float %tmp92, i32 0
%tmp105 = insertelement <4 x float> %tmp104, float %tmp93, i32 1
%tmp106 = insertelement <4 x float> %tmp105, float %tmp94, i32 2
%tmp107 = insertelement <4 x float> %tmp106, float 0.000000e+00, i32 3
- %tmp108 = insertelement <4 x float> undef, float %tmp40, i32 0
+ %tmp108 = insertelement <4 x float> poison, float %tmp40, i32 0
%tmp109 = insertelement <4 x float> %tmp108, float %tmp41, i32 1
%tmp110 = insertelement <4 x float> %tmp109, float %tmp42, i32 2
%tmp111 = insertelement <4 x float> %tmp110, float 0.000000e+00, i32 3
@@ -124,11 +124,11 @@ IF137: ; preds = %main_body
%tmp113 = fsub float -0.000000e+00, %tmp92
%tmp114 = fsub float -0.000000e+00, %tmp93
%tmp115 = fsub float -0.000000e+00, %tmp94
- %tmp116 = insertelement <4 x float> undef, float %tmp34, i32 0
+ %tmp116 = insertelement <4 x float> poison, float %tmp34, i32 0
%tmp117 = insertelement <4 x float> %tmp116, float %tmp35, i32 1
%tmp118 = insertelement <4 x float> %tmp117, float %tmp36, i32 2
%tmp119 = insertelement <4 x float> %tmp118, float 0.000000e+00, i32 3
- %tmp120 = insertelement <4 x float> undef, float %tmp113, i32 0
+ %tmp120 = insertelement <4 x float> poison, float %tmp113, i32 0
%tmp121 = insertelement <4 x float> %tmp120, float %tmp114, i32 1
%tmp122 = insertelement <4 x float> %tmp121, float %tmp115, i32 2
%tmp123 = insertelement <4 x float> %tmp122, float 0.000000e+00, i32 3
@@ -155,7 +155,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp138 = fmul float %tmp26, 0x3F847AE140000000
%tmp139 = fmul float %tmp27, 0x3F847AE140000000
%tmp140 = fmul float %tmp28, 0x3F847AE140000000
- %tmp141 = insertelement <4 x float> undef, float %tmp138, i32 0
+ %tmp141 = insertelement <4 x float> poison, float %tmp138, i32 0
%tmp142 = insertelement <4 x float> %tmp141, float %tmp139, i32 1
%tmp143 = insertelement <4 x float> %tmp142, float %tmp140, i32 2
%tmp144 = insertelement <4 x float> %tmp143, float 0.000000e+00, i32 3
@@ -163,7 +163,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp146 = extractelement <4 x float> %tmp144, i32 1
%tmp147 = extractelement <4 x float> %tmp144, i32 2
%tmp148 = extractelement <4 x float> %tmp144, i32 3
- %tmp149 = insertelement <4 x float> undef, float %tmp145, i32 0
+ %tmp149 = insertelement <4 x float> poison, float %tmp145, i32 0
%tmp150 = insertelement <4 x float> %tmp149, float %tmp146, i32 1
%tmp151 = insertelement <4 x float> %tmp150, float %tmp147, i32 2
%tmp152 = insertelement <4 x float> %tmp151, float %tmp148, i32 3
@@ -176,7 +176,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp159 = fmul float %tmp26, 0x3F45A07B40000000
%tmp160 = fmul float %tmp27, 0x3F45A07B40000000
%tmp161 = fmul float %tmp28, 0x3F45A07B40000000
- %tmp162 = insertelement <4 x float> undef, float %tmp159, i32 0
+ %tmp162 = insertelement <4 x float> poison, float %tmp159, i32 0
%tmp163 = insertelement <4 x float> %tmp162, float %tmp160, i32 1
%tmp164 = insertelement <4 x float> %tmp163, float %tmp161, i32 2
%tmp165 = insertelement <4 x float> %tmp164, float 0.000000e+00, i32 3
@@ -184,7 +184,7 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp167 = extractelement <4 x float> %tmp165, i32 1
%tmp168 = extractelement <4 x float> %tmp165, i32 2
%tmp169 = extractelement <4 x float> %tmp165, i32 3
- %tmp170 = insertelement <4 x float> undef, float %tmp166, i32 0
+ %tmp170 = insertelement <4 x float> poison, float %tmp166, i32 0
%tmp171 = insertelement <4 x float> %tmp170, float %tmp167, i32 1
%tmp172 = insertelement <4 x float> %tmp171, float %tmp168, i32 2
%tmp173 = insertelement <4 x float> %tmp172, float %tmp169, i32 3
@@ -251,28 +251,28 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp227 = fmul float %clamp.i14, %tmp226
%tmp228 = fmul float %tmp26, 0x3F368B5CC0000000
%tmp229 = fmul float %tmp27, 0x3F368B5CC0000000
- %tmp230 = insertelement <4 x float> undef, float %tmp228, i32 0
+ %tmp230 = insertelement <4 x float> poison, float %tmp228, i32 0
%tmp231 = insertelement <4 x float> %tmp230, float %tmp229, i32 1
%tmp232 = insertelement <4 x float> %tmp231, float 0.000000e+00, i32 2
%tmp233 = insertelement <4 x float> %tmp232, float 0.000000e+00, i32 3
%tmp234 = extractelement <4 x float> %tmp233, i32 0
%tmp235 = extractelement <4 x float> %tmp233, i32 1
- %tmp236 = insertelement <4 x float> undef, float %tmp234, i32 0
+ %tmp236 = insertelement <4 x float> poison, float %tmp234, i32 0
%tmp237 = insertelement <4 x float> %tmp236, float %tmp235, i32 1
- %tmp238 = insertelement <4 x float> %tmp237, float undef, i32 2
- %tmp239 = insertelement <4 x float> %tmp238, float undef, i32 3
+ %tmp238 = insertelement <4 x float> %tmp237, float poison, i32 2
+ %tmp239 = insertelement <4 x float> %tmp238, float poison, i32 3
%tmp240 = shufflevector <4 x float> %tmp239, <4 x float> %tmp239, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp241 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp240, i32 0, i32 0, i32 0, i32 17, i32 1, i32 1, i32 1, i32 1, i32 1)
%tmp242 = extractelement <4 x float> %tmp241, i32 0
- %tmp243 = insertelement <4 x float> undef, float %tmp242, i32 0
+ %tmp243 = insertelement <4 x float> poison, float %tmp242, i32 0
%tmp244 = insertelement <4 x float> %tmp243, float %tmp229, i32 1
%tmp245 = insertelement <4 x float> %tmp244, float 0.000000e+00, i32 2
%tmp246 = insertelement <4 x float> %tmp245, float 0.000000e+00, i32 3
%tmp247 = extractelement <4 x float> %tmp246, i32 0
- %tmp248 = insertelement <4 x float> undef, float %tmp247, i32 0
- %tmp249 = insertelement <4 x float> %tmp248, float undef, i32 1
- %tmp250 = insertelement <4 x float> %tmp249, float undef, i32 2
- %tmp251 = insertelement <4 x float> %tmp250, float undef, i32 3
+ %tmp248 = insertelement <4 x float> poison, float %tmp247, i32 0
+ %tmp249 = insertelement <4 x float> %tmp248, float poison, i32 1
+ %tmp250 = insertelement <4 x float> %tmp249, float poison, i32 2
+ %tmp251 = insertelement <4 x float> %tmp250, float poison, i32 3
%tmp252 = shufflevector <4 x float> %tmp251, <4 x float> %tmp251, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp253 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp252, i32 0, i32 0, i32 0, i32 18, i32 2, i32 1, i32 1, i32 1, i32 1)
%tmp254 = extractelement <4 x float> %tmp253, i32 0
@@ -312,16 +312,16 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp285 = fmul float %clamp.i8, %tmp284
%tmp286 = fmul float %tmp26, 0x3F22DFD6A0000000
%tmp287 = fmul float %tmp27, 0x3F22DFD6A0000000
- %tmp288 = insertelement <4 x float> undef, float %tmp286, i32 0
+ %tmp288 = insertelement <4 x float> poison, float %tmp286, i32 0
%tmp289 = insertelement <4 x float> %tmp288, float %tmp287, i32 1
%tmp290 = insertelement <4 x float> %tmp289, float 0.000000e+00, i32 2
%tmp291 = insertelement <4 x float> %tmp290, float 0.000000e+00, i32 3
%tmp292 = extractelement <4 x float> %tmp291, i32 0
%tmp293 = extractelement <4 x float> %tmp291, i32 1
- %tmp294 = insertelement <4 x float> undef, float %tmp292, i32 0
+ %tmp294 = insertelement <4 x float> poison, float %tmp292, i32 0
%tmp295 = insertelement <4 x float> %tmp294, float %tmp293, i32 1
- %tmp296 = insertelement <4 x float> %tmp295, float undef, i32 2
- %tmp297 = insertelement <4 x float> %tmp296, float undef, i32 3
+ %tmp296 = insertelement <4 x float> %tmp295, float poison, i32 2
+ %tmp297 = insertelement <4 x float> %tmp296, float poison, i32 3
%tmp298 = shufflevector <4 x float> %tmp297, <4 x float> %tmp297, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp299 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp298, i32 0, i32 0, i32 0, i32 19, i32 3, i32 1, i32 1, i32 1, i32 1)
%tmp300 = extractelement <4 x float> %tmp299, i32 0
@@ -347,11 +347,11 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp320 = fadd float %tmp319, %tmp314
%tmp321 = fmul float %temp70.0, %tmp36
%tmp322 = fadd float %tmp321, %tmp316
- %tmp323 = insertelement <4 x float> undef, float %tmp318, i32 0
+ %tmp323 = insertelement <4 x float> poison, float %tmp318, i32 0
%tmp324 = insertelement <4 x float> %tmp323, float %tmp320, i32 1
%tmp325 = insertelement <4 x float> %tmp324, float %tmp322, i32 2
%tmp326 = insertelement <4 x float> %tmp325, float 0.000000e+00, i32 3
- %tmp327 = insertelement <4 x float> undef, float %tmp318, i32 0
+ %tmp327 = insertelement <4 x float> poison, float %tmp318, i32 0
%tmp328 = insertelement <4 x float> %tmp327, float %tmp320, i32 1
%tmp329 = insertelement <4 x float> %tmp328, float %tmp322, i32 2
%tmp330 = insertelement <4 x float> %tmp329, float 0.000000e+00, i32 3
@@ -380,11 +380,11 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp353 = fsub float -0.000000e+00, %result.i
%tmp354 = fsub float -0.000000e+00, %tmp347
%tmp355 = fadd float %tmp353, %tmp354
- %tmp356 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp356 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp357 = insertelement <4 x float> %tmp356, float %tmp44, i32 1
%tmp358 = insertelement <4 x float> %tmp357, float %tmp45, i32 2
%tmp359 = insertelement <4 x float> %tmp358, float 0.000000e+00, i32 3
- %tmp360 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp360 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp361 = insertelement <4 x float> %tmp360, float %tmp44, i32 1
%tmp362 = insertelement <4 x float> %tmp361, float %tmp45, i32 2
%tmp363 = insertelement <4 x float> %tmp362, float 0.000000e+00, i32 3
@@ -407,11 +407,11 @@ ENDIF136: ; preds = %ENDIF154, %main_bod
%tmp379 = fsub float -0.000000e+00, %result.i
%tmp380 = fsub float -0.000000e+00, %tmp347
%tmp381 = fadd float %tmp379, %tmp380
- %tmp382 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp382 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp383 = insertelement <4 x float> %tmp382, float %tmp44, i32 1
%tmp384 = insertelement <4 x float> %tmp383, float %tmp45, i32 2
%tmp385 = insertelement <4 x float> %tmp384, float 0.000000e+00, i32 3
- %tmp386 = insertelement <4 x float> undef, float %tmp43, i32 0
+ %tmp386 = insertelement <4 x float> poison, float %tmp43, i32 0
%tmp387 = insertelement <4 x float> %tmp386, float %tmp44, i32 1
%tmp388 = insertelement <4 x float> %tmp387, float %tmp45, i32 2
%tmp389 = insertelement <4 x float> %tmp388, float 0.000000e+00, i32 3
@@ -492,16 +492,16 @@ IF140: ; preds = %LOOP
%tmp422 = fadd float %tmp421, %tmp22
%tmp423 = fmul float %tmp130, %temp92.0
%tmp424 = fadd float %tmp423, %tmp23
- %tmp425 = insertelement <4 x float> undef, float %tmp422, i32 0
+ %tmp425 = insertelement <4 x float> poison, float %tmp422, i32 0
%tmp426 = insertelement <4 x float> %tmp425, float %tmp424, i32 1
%tmp427 = insertelement <4 x float> %tmp426, float 0.000000e+00, i32 2
%tmp428 = insertelement <4 x float> %tmp427, float 0.000000e+00, i32 3
%tmp429 = extractelement <4 x float> %tmp428, i32 0
%tmp430 = extractelement <4 x float> %tmp428, i32 1
- %tmp431 = insertelement <4 x float> undef, float %tmp429, i32 0
+ %tmp431 = insertelement <4 x float> poison, float %tmp429, i32 0
%tmp432 = insertelement <4 x float> %tmp431, float %tmp430, i32 1
- %tmp433 = insertelement <4 x float> %tmp432, float undef, i32 2
- %tmp434 = insertelement <4 x float> %tmp433, float undef, i32 3
+ %tmp433 = insertelement <4 x float> %tmp432, float poison, i32 2
+ %tmp434 = insertelement <4 x float> %tmp433, float poison, i32 3
%tmp435 = shufflevector <4 x float> %tmp434, <4 x float> %tmp434, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%tmp436 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp435, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1)
%tmp437 = extractelement <4 x float> %tmp436, i32 3
@@ -518,16 +518,16 @@ ENDIF139: ; preds = %LOOP
%tmp445 = fadd float %tmp444, %tmp22
%tmp446 = fmul float %tmp130, %tmp443
%tmp447 = fadd float %tmp446, %tmp23
- %tmp448 = insertelement <4 x float> undef, float %tmp445, i32 0
+ %tmp448 = insertelement <4 x float> poison, float %tmp445, i32 0
%tmp449 = insertelement <4 x float> %tmp448, float %tmp447, i32 1
%tmp450 = insertelement <4 x float> %tmp449, float 0.000000e+00, i32 2
%tmp451 = insertelement <4 x float> %tmp450, float 0.000000e+00, i32 3
%tmp452 = extractelement <4 x float> %tmp451, i32 0
%tmp453 = extractelement <4 x float> %tmp451, i32 1
- %tmp454 = insertelement <4 x float> undef, float %tmp452, i32 0
+ %tmp454 = insertelement <4 x float> poison, float %tmp452, i32 0
%tmp455 = insertelement <4 x float> %tmp454, float %tmp453, i32 1
- %tmp456 = insertelement <4 x float> %tmp455, float undef, i32 2
- %tmp4...
[truncated]
|
You can test this locally with the following command:git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 5a0a2f8239d34332000009a05e7972f0303ac746 e980e7c880682dd9905c12222fb06b7e278ae03b llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll llvm/test/CodeGen/AMDGPU/add3.ll llvm/test/CodeGen/AMDGPU/amdpal_scratch_mergedshader.ll llvm/test/CodeGen/AMDGPU/any_extend_vector_inreg.ll llvm/test/CodeGen/AMDGPU/anyext.ll llvm/test/CodeGen/AMDGPU/bf16-conversions.ll llvm/test/CodeGen/AMDGPU/bfi_nested.ll llvm/test/CodeGen/AMDGPU/big_alu.ll llvm/test/CodeGen/AMDGPU/bug-deadlanes.ll llvm/test/CodeGen/AMDGPU/bug-v4f64-subvector.ll llvm/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll llvm/test/CodeGen/AMDGPU/build-vector-packed-partial-undef.ll llvm/test/CodeGen/AMDGPU/build_vector-r600.ll llvm/test/CodeGen/AMDGPU/build_vector.ll llvm/test/CodeGen/AMDGPU/bypass-div.ll llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll llvm/test/CodeGen/AMDGPU/coalescer_remat.ll llvm/test/CodeGen/AMDGPU/collapse-endcf.ll llvm/test/CodeGen/AMDGPU/complex-folding.ll llvm/test/CodeGen/AMDGPU/cube.ll llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll llvm/test/CodeGen/AMDGPU/dagcomb-shuffle-vecextend-non2.ll llvm/test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll llvm/test/CodeGen/AMDGPU/dead-machine-elim-after-dead-lane.ll llvm/test/CodeGen/AMDGPU/debug-value.ll llvm/test/CodeGen/AMDGPU/debug-value2.ll llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll llvm/test/CodeGen/AMDGPU/ds_read2.ll llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll llvm/test/CodeGen/AMDGPU/ds_write2.ll llvm/test/CodeGen/AMDGPU/extract-subvector-equal-length.ll llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll llvm/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll llvm/test/CodeGen/AMDGPU/flat-offset-bug.ll llvm/test/CodeGen/AMDGPU/floor.ll llvm/test/CodeGen/AMDGPU/fmac.sdwa.ll llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll llvm/test/CodeGen/AMDGPU/fmad.ll llvm/test/CodeGen/AMDGPU/fmax.ll llvm/test/CodeGen/AMDGPU/fmin.ll llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll llvm/test/CodeGen/AMDGPU/fneg-combines.ll llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll llvm/test/CodeGen/AMDGPU/function-returns.ll llvm/test/CodeGen/AMDGPU/global-load-saddr-to-vaddr.ll llvm/test/CodeGen/AMDGPU/global-saddr-load.ll llvm/test/CodeGen/AMDGPU/image-schedule.ll llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll llvm/test/CodeGen/AMDGPU/input-mods.r600.ll llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll llvm/test/CodeGen/AMDGPU/jump-address.ll llvm/test/CodeGen/AMDGPU/kcache-fold.ll llvm/test/CodeGen/AMDGPU/lds-bounds.ll llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.nsa.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.udot2.ll llvm/test/CodeGen/AMDGPU/llvm.pow.ll llvm/test/CodeGen/AMDGPU/llvm.r600.cube.ll llvm/test/CodeGen/AMDGPU/load-hi16.ll llvm/test/CodeGen/AMDGPU/load-input-fold.ll llvm/test/CodeGen/AMDGPU/load-lo16.ll llvm/test/CodeGen/AMDGPU/loop-live-out-copy-undef-subrange.ll llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll llvm/test/CodeGen/AMDGPU/mad_uint24.ll llvm/test/CodeGen/AMDGPU/max-literals.ll llvm/test/CodeGen/AMDGPU/memory_clause.ll llvm/test/CodeGen/AMDGPU/merge-store-crash.ll llvm/test/CodeGen/AMDGPU/mfma-loop.ll llvm/test/CodeGen/AMDGPU/nsa-reassign.ll llvm/test/CodeGen/AMDGPU/operand-folding.ll llvm/test/CodeGen/AMDGPU/pack.v2f16.ll llvm/test/CodeGen/AMDGPU/pack.v2i16.ll llvm/test/CodeGen/AMDGPU/packed-fp32.ll llvm/test/CodeGen/AMDGPU/packed-op-sel.ll llvm/test/CodeGen/AMDGPU/predicate-dp4.ll llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll llvm/test/CodeGen/AMDGPU/pv-packing.ll llvm/test/CodeGen/AMDGPU/pv.ll llvm/test/CodeGen/AMDGPU/r600-encoding.ll llvm/test/CodeGen/AMDGPU/r600-export-fix.ll llvm/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll llvm/test/CodeGen/AMDGPU/r600cfg.ll llvm/test/CodeGen/AMDGPU/reassoc-scalar.ll llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll llvm/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll llvm/test/CodeGen/AMDGPU/schedule-fs-loop.ll llvm/test/CodeGen/AMDGPU/schedule-if-2.ll llvm/test/CodeGen/AMDGPU/schedule-if.ll llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll llvm/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll llvm/test/CodeGen/AMDGPU/scheduler-subrange-crash.ll llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll llvm/test/CodeGen/AMDGPU/sgpr-copy-duplicate-operand.ll llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll llvm/test/CodeGen/AMDGPU/si-vector-hang.ll llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll llvm/test/CodeGen/AMDGPU/smfmac_no_agprs.ll llvm/test/CodeGen/AMDGPU/sminmax.ll llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll llvm/test/CodeGen/AMDGPU/smrd.ll llvm/test/CodeGen/AMDGPU/spill-vector-superclass.ll llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll llvm/test/CodeGen/AMDGPU/subreg-eliminate-dead.ll llvm/test/CodeGen/AMDGPU/swizzle-export.ll llvm/test/CodeGen/AMDGPU/tex-clause-antidep.ll llvm/test/CodeGen/AMDGPU/texture-input-merge.ll llvm/test/CodeGen/AMDGPU/trunc-combine.ll llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll llvm/test/CodeGen/AMDGPU/unpack-half.ll llvm/test/CodeGen/AMDGPU/v_pack.ll llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll llvm/test/CodeGen/AMDGPU/xor3.llThe following files introduce new uses of undef:
Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields In tests, avoid using For example, this is considered a bad practice: define void @fn() {
...
br i1 undef, ...
}Please use the following instead: define void @fn(i1 %cond) {
...
br i1 %cond, ...
}Please refer to the Undefined Behavior Manual for more information. |
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This is the bulk update with perl, with cases which require additional update left for later.
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…30896) This is the bulk update with perl, with cases which require additional update left for later.
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This is the bulk update with perl, with cases which require additional
update left for later.