AMDGPU: Replace ptr undef in tests with poison #131050

arsenm · 2025-03-13T01:26:32Z

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arsenm · 2025-03-13T01:26:50Z

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llvmbot · 2025-03-13T01:27:30Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Patch is 45.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/131050.diff

31 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll (+12-12)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll (+4-4)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll (+5-5)
(modified) llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll (+12-12)
(modified) llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll (+3-3)
(modified) llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll (+4-4)
(modified) llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll (+10-10)
(modified) llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/offset-split-flat.ll (+25-25)
(modified) llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/opencl-printf.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll (+3-3)
(modified) llvm/test/CodeGen/AMDGPU/swdev282079.ll (+1-1)
(modified) llvm/test/CodeGen/AMDGPU/swdev373493.ll (+2-2)
(modified) llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll (+1-1)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
index 11c17c21e189d..63009bdc2643f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
@@ -58,7 +58,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -141,7 +141,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -224,7 +224,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -307,7 +307,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -390,7 +390,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -473,7 +473,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -556,7 +556,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -639,7 +639,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -722,7 +722,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -805,7 +805,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -888,7 +888,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -971,7 +971,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
index bba0e08ee6341..d66f50bf04770 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
@@ -735,7 +735,7 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
   %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
   %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -839,7 +839,7 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
   %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
   %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -921,7 +921,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
   %ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
   %ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
 
@@ -995,6 +995,6 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
   %ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
   %ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
   %v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
-  store <4 x i32> %v, ptr undef
+  store <4 x i32> %v, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
index d59c5a6a2609c..328849a9cea20 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
@@ -11,7 +11,7 @@ declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i3
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -20,6 +20,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
index 798a3ee1d75fd..b46a82759f6c5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
@@ -11,7 +11,7 @@ declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -20,6 +20,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
index 89daf3ae88cbc..95aa339a05ecd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
@@ -12,7 +12,7 @@ declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -21,6 +21,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
index 5b0b91f983fe6..d55cd96f6d7cd 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
@@ -12,7 +12,7 @@ declare <2 x half> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2f16(<2 x half>,
 define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store float %ret, ptr undef
+  store float %ret, ptr poison
   ret void
 }
 
@@ -21,6 +21,6 @@ main_body:
 define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
 main_body:
   %ret = call <2 x half> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
-  store <2 x half> %ret, ptr undef
+  store <2 x half> %ret, ptr poison
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
index dd2f26f7b73a1..ad588ebee2f9e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
@@ -105,7 +105,7 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) {
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    s_endpgm
   %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
-  store volatile double %result, ptr undef
+  store volatile double %result, ptr poison
   ret void
 }
 
@@ -167,7 +167,7 @@ define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {
 ; GFX11-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX11-NEXT:    s_endpgm
   %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
-  store volatile double %result, ptr undef
+  store volatile double %result, ptr poison
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll
index f1d6a848848c1..95a3263a58a2b 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll
@@ -70,7 +70,7 @@ define amdgpu_kernel void @addrspacecast_flat_undef_to_local(ptr addrspace(1) %o
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    CF_END
 ; CHECK-NEXT:    PAD
-  store ptr addrspace(3) addrspacecast (ptr undef to ptr addrspace(3)), ptr addrspace(1) %out
+  store ptr addrspace(3) addrspacecast (ptr poison to ptr addrspace(3)), ptr addrspace(1) %out
   ret void
 }
 
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
index 6b935a8768d3d..5d438887cbc91 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
@@ -176,7 +176,7 @@ define void @test_7_7(ptr addrspace(7) %p, ptr addrspace(7) %p1) {
   ret void
 }
 
-@cst = internal addrspace(4) global ptr undef, align 4
+@cst = internal addrspace(4) global ptr poison, align 4
 
 ; CHECK-LABEL: Function: test_8_0
 ; CHECK-DAG: NoAlias:   i8 addrspace(3)* %p, i8* %p1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
index b34df3ffca264..2ac5c78d8cdb5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll
@@ -162,7 +162,7 @@ entry:
   br label %bb.1
 
 bb.1:
-  store float 1.0, ptr undef
+  store float 1.0, ptr poison
   br label %bb.2
 
 bb.2:
diff --git a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
index 41e136624d7d2..24b695283de4a 100644
--- a/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll
@@ -68,7 +68,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 {
 ;  %x.3 = call i64 @llvm.amdgcn.dispatch.id()
 ;  %x.4 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
 ;  %x.5 = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
-;  store volatile i32 0, ptr undef
+;  store volatile i32 0, ptr poison
 ;  br label %stores
 ;
 ;stores:
@@ -99,7 +99,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 {
 ;                                        ptr addrspace(1) %out3,
 ;                                        ptr addrspace(1) %out4,
 ;                                        i32 %one, i32 %two, i32 %three, i32 %four) #2 {
-;  store volatile i32 0, ptr undef
+;  store volatile i32 0, ptr poison
 ;  %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
 ;  store volatile i32 %x.0, ptr addrspace(1) poison
 ;  %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
index 6b1ecc9dffdb7..2e843048bee16 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
@@ -14,7 +14,7 @@ define amdgpu_kernel void @eq_t(float %x) {
   %s1 = select i1 %c1, i32 56789, i32 1
   %c2 = icmp eq i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -31,7 +31,7 @@ define amdgpu_kernel void @ne_t(float %x) {
   %s1 = select i1 %c1, i32 56789, i32 1
   %c2 = icmp ne i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -48,7 +48,7 @@ define amdgpu_kernel void @eq_f(float %x) {
   %s1 = select i1 %c1, i32 1, i32 56789
   %c2 = icmp eq i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -65,7 +65,7 @@ define amdgpu_kernel void @ne_f(float %x) {
   %s1 = select i1 %c1, i32 1, i32 56789
   %c2 = icmp ne i32 %s1, 56789
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
 
@@ -79,6 +79,6 @@ define amdgpu_kernel void @different_constants(float %x) {
   %s1 = select i1 %c1, i32 56789, i32 1
   %c2 = icmp eq i32 %s1, 5678
   %s2 = select i1 %c2, float 4.0, float 2.0
-  store float %s2, ptr undef, align 4
+  store float %s2, ptr poison, align 4
   ret void
 }
diff --git a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
index 7ce49d2966516..873fceedd7b72 100644
--- a/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
@@ -59,7 +59,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -142,7 +142,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -225,7 +225,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -308,7 +308,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -391,7 +391,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -474,7 +474,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -557,7 +557,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
-  store double %ret, ptr undef
+  store double %ret, ptr poison
   ret void
 }
 
@@ -640,7 +640,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
 ; GFX942-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i3...
[truncated]

github-actions · 2025-03-13T01:29:53Z

⚠️ undef deprecator found issues in your code. ⚠️

You can test this locally with the following command:

git diff -U0 --pickaxe-regex -S '([^a-zA-Z0-9#_-]undef[^a-zA-Z0-9_-]|UndefValue::get)' 236c18874f96f8b41e1f890d8f9d8671138b766e 4917d4616cc014052e6e1f90d9bae00a79370d96 llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll llvm/test/CodeGen/AMDGPU/gfx90a-enc.ll llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll llvm/test/CodeGen/AMDGPU/offset-split-flat.ll llvm/test/CodeGen/AMDGPU/opencl-printf-and-hostcall.ll llvm/test/CodeGen/AMDGPU/opencl-printf.ll llvm/test/CodeGen/AMDGPU/packed-fp32.ll llvm/test/CodeGen/AMDGPU/propagate-attributes-bitcast-function.ll llvm/test/CodeGen/AMDGPU/propagate-flat-work-group-size.ll llvm/test/CodeGen/AMDGPU/propagate-waves-per-eu.ll llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll llvm/test/CodeGen/AMDGPU/swdev282079.ll llvm/test/CodeGen/AMDGPU/swdev373493.ll llvm/test/CodeGen/AMDGPU/switch-default-block-unreachable.ll

The following files introduce new uses of undef:

llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
llvm/test/CodeGen/AMDGPU/opencl-printf.ll

Undef is now deprecated and should only be used in the rare cases where no replacement is possible. For example, a load of uninitialized memory yields undef. You should use poison values for placeholders instead.

In tests, avoid using undef and having tests that trigger undefined behavior. If you need an operand with some unimportant value, you can add a new argument to the function and use that instead.

For example, this is considered a bad practice:

define void @fn() {
  ...
  br i1 undef, ...
}

Please use the following instead:

define void @fn(i1 %cond) {
  ...
  br i1 %cond, ...
}

Please refer to the Undefined Behavior Manual for more information.

arsenm · 2025-03-13T06:24:35Z

Merge activity

Mar 13, 2:24 AM EDT: A user started a stack merge that includes this pull request via Graphite.
Mar 13, 2:29 AM EDT: Graphite rebased this pull request as part of a merge.
Mar 13, 2:32 AM EDT: Graphite rebased this pull request as part of a merge.
Mar 13, 2:34 AM EDT: A user merged this pull request with Graphite.

This was referenced Mar 13, 2025

AMDGPU: Replace some undef uses in test metadata with poison #131052

Merged

AMDGPU: Replace undef global initializers in tests with poison #131051

Merged

arsenm added backend:AMDGPU llvm:globalisel labels Mar 13, 2025 — with Graphite App

arsenm requested review from jayfoad, krzysz00 and shiltian March 13, 2025 01:27

arsenm marked this pull request as ready for review March 13, 2025 01:27

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-p3-undef-with-poison branch from 5662582 to 236c188 Compare March 13, 2025 01:39

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-p0-undef-with-poison branch from 6b657b1 to 4917d46 Compare March 13, 2025 01:40

shiltian approved these changes Mar 13, 2025

View reviewed changes

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-p3-undef-with-poison branch from 236c188 to 23a1055 Compare March 13, 2025 06:26

Base automatically changed from users/arsenm/amdgpu/tests-replace-p3-undef-with-poison to main March 13, 2025 06:28

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-p0-undef-with-poison branch from 4917d46 to b171643 Compare March 13, 2025 06:29

AMDGPU: Replace ptr undef in tests with poison

9d2e89a

arsenm force-pushed the users/arsenm/amdgpu/tests-replace-p0-undef-with-poison branch from b171643 to 9d2e89a Compare March 13, 2025 06:31

arsenm merged commit 7811075 into main Mar 13, 2025
5 of 10 checks passed

arsenm deleted the users/arsenm/amdgpu/tests-replace-p0-undef-with-poison branch March 13, 2025 06:34

frederik-h pushed a commit to frederik-h/llvm-project that referenced this pull request Mar 18, 2025

AMDGPU: Replace ptr undef in tests with poison (llvm#131050)

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