Add RISC-V CPU type and CPU subtype to llvm & lldb #136785

JDevlieghere · 2025-04-22T23:22:24Z

Add the enum values for RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

llvmbot · 2025-04-22T23:22:57Z

@llvm/pr-subscribers-llvm-binary-utilities

Author: Jonas Devlieghere (JDevlieghere)

Changes

Add the enum values for RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

Full diff: https://github.com/llvm/llvm-project/pull/136785.diff

3 Files Affected:

(modified) lldb/source/Utility/ArchSpec.cpp (+2)
(modified) lldb/unittests/Utility/ArchSpecTest.cpp (+8)
(modified) llvm/include/llvm/BinaryFormat/MachO.h (+7-1)

diff --git a/lldb/source/Utility/ArchSpec.cpp b/lldb/source/Utility/ArchSpec.cpp
index 495215459336a..2e6c6a6ffcbe4 100644
--- a/lldb/source/Utility/ArchSpec.cpp
+++ b/lldb/source/Utility/ArchSpec.cpp
@@ -353,6 +353,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_ARCH1,     UINT32_MAX, SUBTYPE_MASK},
     {ArchSpec::eCore_x86_64_x86_64h,  llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_H,      UINT32_MAX, SUBTYPE_MASK},
     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     CPU_ANY, UINT32_MAX, UINT32_MAX},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      llvm::MachO::CPU_SUBTYPE_RISCV_ALL,     UINT32_MAX, SUBTYPE_MASK},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
     // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
     {ArchSpec::eCore_uknownMach32,    0,                                0,                                      0xFF000000u, 0x00000000u},
     {ArchSpec::eCore_uknownMach64,    llvm::MachO::CPU_ARCH_ABI64,      0,                                      0xFF000000u, 0x00000000u}};
diff --git a/lldb/unittests/Utility/ArchSpecTest.cpp b/lldb/unittests/Utility/ArchSpecTest.cpp
index 2c78629849c64..3bf1c3f81876f 100644
--- a/lldb/unittests/Utility/ArchSpecTest.cpp
+++ b/lldb/unittests/Utility/ArchSpecTest.cpp
@@ -113,6 +113,14 @@ TEST(ArchSpecTest, TestSetTriple) {
                   .consume_front("powerpc-apple-darwin"));
   EXPECT_EQ(ArchSpec::eCore_ppc_ppc970, AS.GetCore());
 
+  AS = ArchSpec();
+  EXPECT_TRUE(AS.SetTriple("24-0-apple-unknown"));
+  EXPECT_EQ(uint32_t(llvm::MachO::CPU_TYPE_RISCV), AS.GetMachOCPUType());
+  EXPECT_EQ(0u, AS.GetMachOCPUSubType());
+  EXPECT_TRUE(llvm::StringRef(AS.GetTriple().str())
+                  .consume_front("riscv32-apple-unknown"));
+  EXPECT_EQ(ArchSpec::eCore_riscv32, AS.GetCore());
+
   AS = ArchSpec();
   EXPECT_TRUE(AS.SetTriple("i686-pc-windows"));
   EXPECT_EQ(llvm::Triple::x86, AS.GetTriple().getArch());
diff --git a/llvm/include/llvm/BinaryFormat/MachO.h b/llvm/include/llvm/BinaryFormat/MachO.h
index 83aaf19c71e50..5afe70bffc24b 100644
--- a/llvm/include/llvm/BinaryFormat/MachO.h
+++ b/llvm/include/llvm/BinaryFormat/MachO.h
@@ -1571,7 +1571,9 @@ enum CPUType {
   CPU_TYPE_ARM64_32 = CPU_TYPE_ARM | CPU_ARCH_ABI64_32,
   CPU_TYPE_SPARC = 14,
   CPU_TYPE_POWERPC = 18,
-  CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
+  CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64,
+
+  CPU_TYPE_RISCV = 24,
 };
 
 enum : uint32_t {
@@ -1698,6 +1700,10 @@ enum CPUSubTypePowerPC {
   CPU_SUBTYPE_MC98601 = CPU_SUBTYPE_POWERPC_601
 };
 
+enum CPUSubTypeRISCV {
+  CPU_SUBTYPE_RISCV_ALL = 0,
+};
+
 Expected<uint32_t> getCPUType(const Triple &T);
 Expected<uint32_t> getCPUSubType(const Triple &T);
 Expected<uint32_t> getCPUSubType(const Triple &T, unsigned PtrAuthABIVersion,

llvmbot · 2025-04-22T23:22:58Z

@llvm/pr-subscribers-lldb

Author: Jonas Devlieghere (JDevlieghere)

Changes

Add the enum values for RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

Full diff: https://github.com/llvm/llvm-project/pull/136785.diff

3 Files Affected:

(modified) lldb/source/Utility/ArchSpec.cpp (+2)
(modified) lldb/unittests/Utility/ArchSpecTest.cpp (+8)
(modified) llvm/include/llvm/BinaryFormat/MachO.h (+7-1)

diff --git a/lldb/source/Utility/ArchSpec.cpp b/lldb/source/Utility/ArchSpec.cpp
index 495215459336a..2e6c6a6ffcbe4 100644
--- a/lldb/source/Utility/ArchSpec.cpp
+++ b/lldb/source/Utility/ArchSpec.cpp
@@ -353,6 +353,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_ARCH1,     UINT32_MAX, SUBTYPE_MASK},
     {ArchSpec::eCore_x86_64_x86_64h,  llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_H,      UINT32_MAX, SUBTYPE_MASK},
     {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     CPU_ANY, UINT32_MAX, UINT32_MAX},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      llvm::MachO::CPU_SUBTYPE_RISCV_ALL,     UINT32_MAX, SUBTYPE_MASK},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      CPU_ANY,                                UINT32_MAX, SUBTYPE_MASK},
     // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
     {ArchSpec::eCore_uknownMach32,    0,                                0,                                      0xFF000000u, 0x00000000u},
     {ArchSpec::eCore_uknownMach64,    llvm::MachO::CPU_ARCH_ABI64,      0,                                      0xFF000000u, 0x00000000u}};
diff --git a/lldb/unittests/Utility/ArchSpecTest.cpp b/lldb/unittests/Utility/ArchSpecTest.cpp
index 2c78629849c64..3bf1c3f81876f 100644
--- a/lldb/unittests/Utility/ArchSpecTest.cpp
+++ b/lldb/unittests/Utility/ArchSpecTest.cpp
@@ -113,6 +113,14 @@ TEST(ArchSpecTest, TestSetTriple) {
                   .consume_front("powerpc-apple-darwin"));
   EXPECT_EQ(ArchSpec::eCore_ppc_ppc970, AS.GetCore());
 
+  AS = ArchSpec();
+  EXPECT_TRUE(AS.SetTriple("24-0-apple-unknown"));
+  EXPECT_EQ(uint32_t(llvm::MachO::CPU_TYPE_RISCV), AS.GetMachOCPUType());
+  EXPECT_EQ(0u, AS.GetMachOCPUSubType());
+  EXPECT_TRUE(llvm::StringRef(AS.GetTriple().str())
+                  .consume_front("riscv32-apple-unknown"));
+  EXPECT_EQ(ArchSpec::eCore_riscv32, AS.GetCore());
+
   AS = ArchSpec();
   EXPECT_TRUE(AS.SetTriple("i686-pc-windows"));
   EXPECT_EQ(llvm::Triple::x86, AS.GetTriple().getArch());
diff --git a/llvm/include/llvm/BinaryFormat/MachO.h b/llvm/include/llvm/BinaryFormat/MachO.h
index 83aaf19c71e50..5afe70bffc24b 100644
--- a/llvm/include/llvm/BinaryFormat/MachO.h
+++ b/llvm/include/llvm/BinaryFormat/MachO.h
@@ -1571,7 +1571,9 @@ enum CPUType {
   CPU_TYPE_ARM64_32 = CPU_TYPE_ARM | CPU_ARCH_ABI64_32,
   CPU_TYPE_SPARC = 14,
   CPU_TYPE_POWERPC = 18,
-  CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
+  CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64,
+
+  CPU_TYPE_RISCV = 24,
 };
 
 enum : uint32_t {
@@ -1698,6 +1700,10 @@ enum CPUSubTypePowerPC {
   CPU_SUBTYPE_MC98601 = CPU_SUBTYPE_POWERPC_601
 };
 
+enum CPUSubTypeRISCV {
+  CPU_SUBTYPE_RISCV_ALL = 0,
+};
+
 Expected<uint32_t> getCPUType(const Triple &T);
 Expected<uint32_t> getCPUSubType(const Triple &T);
 Expected<uint32_t> getCPUSubType(const Triple &T, unsigned PtrAuthABIVersion,

jasonmolenda

LGTM.

topperc · 2025-04-23T00:15:52Z

lldb/source/Utility/ArchSpec.cpp

@@ -353,6 +353,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
    {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_ARCH1,     UINT32_MAX, SUBTYPE_MASK},
    {ArchSpec::eCore_x86_64_x86_64h,  llvm::MachO::CPU_TYPE_X86_64,     llvm::MachO::CPU_SUBTYPE_X86_64_H,      UINT32_MAX, SUBTYPE_MASK},
    {ArchSpec::eCore_x86_64_x86_64,   llvm::MachO::CPU_TYPE_X86_64,     CPU_ANY, UINT32_MAX, UINT32_MAX},
+    {ArchSpec::eCore_riscv32,         llvm::MachO::CPU_TYPE_RISCV,      llvm::MachO::CPU_SUBTYPE_RISCV_ALL,     UINT32_MAX, SUBTYPE_MASK},


I don't know this stuff works. Do we need riscv64 too or is it shared?

There isn't a CPU_TYPE for riscv64.

Should we name this eCore_riscv then? Given that it applies to both.

That's not quite accurate. It doesn't apply to both, it is riscv32.

Oh so this is just how it's been named? If you're matching what the MachO spec (whatever form it is) then that's fine, too late to change it now.

And I take from that that at some point a riscv64 value could be allocated for MachO but there is not one at the moment.

Yeah, I can't comment on the future but that's correct.

Cool. Conclusion here is that in this context, CPU_TYPE_RISCV means riscv32. I might have added a 32 on the end there, but it is what it is :)

(though, maybe it was to follow ARM and ARM64)

lldb/unittests/Utility/ArchSpecTest.cpp

DavidSpickett

LGTM

Please note in the commit title that this is specifically for MachO, not for all object file formats.

Add the enum values for MachO RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec. (cherry picked from commit 213424b)

Add the enum values for MachO RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

Add RISC-V CPU type and CPU subtype to llvm & lldb

bb74984

Add the enum values for RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

JDevlieghere requested review from jasonmolenda and fpetrogalli April 22, 2025 23:22

llvmbot added lldb llvm:binary-utilities labels Apr 22, 2025

jasonmolenda approved these changes Apr 22, 2025

View reviewed changes

topperc reviewed Apr 23, 2025

View reviewed changes

DavidSpickett reviewed Apr 23, 2025

View reviewed changes

lldb/unittests/Utility/ArchSpecTest.cpp Show resolved Hide resolved

DavidSpickett approved these changes Apr 23, 2025

View reviewed changes

JDevlieghere merged commit 213424b into llvm:main Apr 23, 2025
14 checks passed

JDevlieghere deleted the riscv-cpu-subtype branch April 23, 2025 18:03

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

Add MachO RISC-V CPU type and CPU subtype to llvm & lldb (llvm#136785)

47ba62e

Add the enum values for MachO RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

Add MachO RISC-V CPU type and CPU subtype to llvm & lldb (llvm#136785)

595570c

Add the enum values for MachO RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

IanWood1 pushed a commit to IanWood1/llvm-project that referenced this pull request May 6, 2025

Add MachO RISC-V CPU type and CPU subtype to llvm & lldb (llvm#136785)

dd86026

Add the enum values for MachO RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec.

fpetrogalli mentioned this pull request May 29, 2025

[RISCV] Add basic Mach-O triple support. #141682

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