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Add RISC-V CPU type and CPU subtype to llvm & lldb #136785

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Merged
merged 1 commit into from
Apr 23, 2025
Merged

Add RISC-V CPU type and CPU subtype to llvm & lldb #136785

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2 changes: 2 additions & 0 deletions lldb/source/Utility/ArchSpec.cpp
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Expand Up @@ -353,6 +353,8 @@ static const ArchDefinitionEntry g_macho_arch_entries[] = {
{ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
{ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
{ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
{ArchSpec::eCore_riscv32, llvm::MachO::CPU_TYPE_RISCV, llvm::MachO::CPU_SUBTYPE_RISCV_ALL, UINT32_MAX, SUBTYPE_MASK},
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I don't know this stuff works. Do we need riscv64 too or is it shared?

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There isn't a CPU_TYPE for riscv64.

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Should we name this eCore_riscv then? Given that it applies to both.

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That's not quite accurate. It doesn't apply to both, it is riscv32.

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Oh so this is just how it's been named? If you're matching what the MachO spec (whatever form it is) then that's fine, too late to change it now.

And I take from that that at some point a riscv64 value could be allocated for MachO but there is not one at the moment.

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Yeah, I can't comment on the future but that's correct.

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Cool. Conclusion here is that in this context, CPU_TYPE_RISCV means riscv32. I might have added a 32 on the end there, but it is what it is :)

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(though, maybe it was to follow ARM and ARM64)

{ArchSpec::eCore_riscv32, llvm::MachO::CPU_TYPE_RISCV, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
// Catch any unknown mach architectures so we can always use the object and symbol mach-o files
{ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
{ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
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8 changes: 8 additions & 0 deletions lldb/unittests/Utility/ArchSpecTest.cpp
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Expand Up @@ -113,6 +113,14 @@ TEST(ArchSpecTest, TestSetTriple) {
.consume_front("powerpc-apple-darwin"));
EXPECT_EQ(ArchSpec::eCore_ppc_ppc970, AS.GetCore());

AS = ArchSpec();
EXPECT_TRUE(AS.SetTriple("24-0-apple-unknown"));
EXPECT_EQ(uint32_t(llvm::MachO::CPU_TYPE_RISCV), AS.GetMachOCPUType());
EXPECT_EQ(0u, AS.GetMachOCPUSubType());
EXPECT_TRUE(llvm::StringRef(AS.GetTriple().str())
.consume_front("riscv32-apple-unknown"));
EXPECT_EQ(ArchSpec::eCore_riscv32, AS.GetCore());

AS = ArchSpec();
EXPECT_TRUE(AS.SetTriple("i686-pc-windows"));
EXPECT_EQ(llvm::Triple::x86, AS.GetTriple().getArch());
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8 changes: 7 additions & 1 deletion llvm/include/llvm/BinaryFormat/MachO.h
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Expand Up @@ -1571,7 +1571,9 @@ enum CPUType {
CPU_TYPE_ARM64_32 = CPU_TYPE_ARM | CPU_ARCH_ABI64_32,
CPU_TYPE_SPARC = 14,
CPU_TYPE_POWERPC = 18,
CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64
CPU_TYPE_POWERPC64 = CPU_TYPE_POWERPC | CPU_ARCH_ABI64,

CPU_TYPE_RISCV = 24,
};

enum : uint32_t {
Expand Down Expand Up @@ -1698,6 +1700,10 @@ enum CPUSubTypePowerPC {
CPU_SUBTYPE_MC98601 = CPU_SUBTYPE_POWERPC_601
};

enum CPUSubTypeRISCV {
CPU_SUBTYPE_RISCV_ALL = 0,
};

Expected<uint32_t> getCPUType(const Triple &T);
Expected<uint32_t> getCPUSubType(const Triple &T);
Expected<uint32_t> getCPUSubType(const Triple &T, unsigned PtrAuthABIVersion,
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