[AArch64] Use vecshiftL64 instead of vecshiftR64 to match scalar SLI imm. #139904
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@llvm/pr-subscribers-backend-aarch64 Author: Ricardo Jesus (rj-jesus) ChangesIt looks like Fixes #139879. Full diff: https://github.com/llvm/llvm-project/pull/139904.diff 2 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 33241c65a4a37..5489541fcb318 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -10188,7 +10188,7 @@ multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm,
def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
FPR64, FPR64, vecshiftL64, asm,
[(set (v1i64 FPR64:$dst), (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
- (i32 vecshiftR64:$imm)))]> {
+ (i32 vecshiftL64:$imm)))]> {
let Inst{21-16} = imm{5-0};
}
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vshift.ll b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
index 2f543cc324bc2..a7f9ca8d73c1f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vshift.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vshift.ll
@@ -95,6 +95,7 @@
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4h
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli2s
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli1d_imm0
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli16b
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli8h
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sli4s
@@ -4088,6 +4089,16 @@ define <1 x i64> @sli1d(ptr %A, ptr %B) nounwind {
ret <1 x i64> %tmp3
}
+; Ensure we can select scalar SLI with a zero shift (see issue #139879).
+define <1 x i64> @sli1d_imm0(<1 x i64> %a, <1 x i64> %b) {
+; CHECK-LABEL: sli1d_imm0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: sli d0, d1, #0
+; CHECK-NEXT: ret
+ %r = call <1 x i64> @llvm.aarch64.neon.vsli(<1 x i64> %a, <1 x i64> %b, i32 0)
+ ret <1 x i64> %r
+}
+
define <16 x i8> @sli16b(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sli16b:
; CHECK: // %bb.0:
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rj-jesus
changed the title
Indeed, would you rather it done here (in this PR) or separately? |
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It can certainly be separate, this makes sense on its own. It is not necessary either way - it is a very minor missed optimization. |
Thanks very much, that makes sense - in that case I'll merge this soon and look into the missed optimisation later. :) |
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@rj-jesus Do you mind having this backported to the release branch? |
Of course, I will do so just now. |
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/cherry-pick e7e4d99 |
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Failed to cherry-pick: e7e4d99 https://github.com/llvm/llvm-project/actions/runs/15041878331 Please manually backport the fix and push it to your github fork. Once this is done, please create a pull request |
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Aah right, that makes sense! In that case, it looks like there's nothing else to do here? |
…imm. (llvm#139904) `SIMDScalarLShiftDTied` should be using `vecshiftL64` to match the immediate argument rather than `vecshiftR64` as the latter prevents the pattern from matching 0 (and allows 64 instead). Fixes llvm#139879.
It looks like
SIMDScalarLShiftDTiedshould be usingvecshiftL64to match the immediate rather thanvecshiftR64, which prevents the pattern from matching 0 (and allows 64 instead).Fixes #139879.