[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT #142603

Pierre-vh · 2025-06-03T13:12:20Z

Test P0 through P6 + P8 for both S/VGPRs.

Pierre-vh · 2025-06-03T13:12:32Z

[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR #142604
[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT #142603 👈 (View in Graphite)
[AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 #142602
[AMDGPU] New RegBanKSelect: Add S128 types #142601
[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule #142560 : 1 other dependent PR (#142600 )
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llvmbot · 2025-06-03T13:14:41Z

@llvm/pr-subscribers-backend-amdgpu

Author: Pierre van Houtryve (Pierre-vh)

Changes

Test P0 through P6 + P8 for both S/VGPRs.

Full diff: https://github.com/llvm/llvm-project/pull/142603.diff

2 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir (+230-6)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir (+228-4)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
index 053aede615f86..42600d7d0dd7a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
@@ -3,29 +3,29 @@
 # RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
-name: inttoptr_s
+name: inttoptr_s_p0
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
-    ; CHECK-LABEL: name: inttoptr_s
+    ; CHECK-LABEL: name: inttoptr_s_p0
     ; CHECK: liveins: $sgpr0_sgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
-    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p0) = G_INTTOPTR [[COPY]](s64)
     %0:_(s64) = COPY $sgpr0_sgpr1
-    %1:_(p4) = G_INTTOPTR %0
+    %1:_(p0) = G_INTTOPTR %0
 ...
 
 ---
-name: inttoptr_v
+name: inttoptr_v_p0
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
-    ; CHECK-LABEL: name: inttoptr_v
+    ; CHECK-LABEL: name: inttoptr_v_p0
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
@@ -33,3 +33,227 @@ body: |
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(p0) = G_INTTOPTR %0
 ...
+
+---
+name: inttoptr_s_p1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: inttoptr_s_p1
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p1) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(p1) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: inttoptr_v_p1
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p1) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p1) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p2
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p2) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p2) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p2
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p2) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p2) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p3
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p3) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p3) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p3
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p3) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p3) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: inttoptr_s_p4
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(p4) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: inttoptr_v_p4
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p4) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p5
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p5) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p5) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p5
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p5) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p5) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p6
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p6) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p6) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p6
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p6) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p6) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-LABEL: name: inttoptr_s_p8
+    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p8) = G_INTTOPTR [[COPY]](s128)
+    %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    %1:_(p8) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-LABEL: name: inttoptr_v_p8
+    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p8) = G_INTTOPTR [[COPY]](s128)
+    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(p8) = G_INTTOPTR %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
index 2db1a5b1d2ba2..9240c9f6df404 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
@@ -3,13 +3,45 @@
 # RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
-name: ptrtoint_s
+name: ptrtoint_s_p0
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
-    ; CHECK-LABEL: name: ptrtoint_s
+    ; CHECK-LABEL: name: ptrtoint_s_p0
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s64) = G_PTRTOINT [[COPY]](p0)
+    %0:_(p0) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p0
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: ptrtoint_v_p0
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s64) = G_PTRTOINT [[COPY]](p0)
+    %0:_(p0) = COPY $vgpr0_vgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: ptrtoint_s_p1
     ; CHECK: liveins: $sgpr0_sgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
@@ -19,13 +51,13 @@ body: |
 ...
 
 ---
-name: ptrtoint_v
+name: ptrtoint_v_p1
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
-    ; CHECK-LABEL: name: ptrtoint_v
+    ; CHECK-LABEL: name: ptrtoint_v_p1
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
@@ -33,3 +65,195 @@ body: |
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s64) = G_PTRTOINT %0
 ...
+
+---
+name: ptrtoint_s_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p2
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p2) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p2)
+    %0:_(p2) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p2
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p2) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p2)
+    %0:_(p2) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p3
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p3)
+    %0:_(p3) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p3
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p3)
+    %0:_(p3) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: ptrtoint_s_p4
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s64) = G_PTRTOINT [[COPY]](p4)
+    %0:_(p4) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: ptrtoint_v_p4
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s64) = G_PTRTOINT [[COPY]](p4)
+    %0:_(p4) = COPY $vgpr0_vgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p5
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p5)
+    %0:_(p5) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p5
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p5)
+    %0:_(p5) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p6
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p6) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p6)
+    %0:_(p6) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p6
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p6) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p6)
+    %0:_(p6) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-LABEL: name: ptrtoint_s_p8
+    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p8) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s128) = G_PTRTOINT [[COPY]](p8)
+    %0:_(p8) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    %1:_(s128) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-LABEL: name: ptrtoint_v_p8
+    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p8) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s128) = G_PTRTOINT [[COPY]](p8)
+    %0:_(p8) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(s128) = G_PTRTOINT %0
+...

llvmbot · 2025-06-03T13:14:41Z

@llvm/pr-subscribers-llvm-globalisel

Author: Pierre van Houtryve (Pierre-vh)

Changes

Test P0 through P6 + P8 for both S/VGPRs.

Full diff: https://github.com/llvm/llvm-project/pull/142603.diff

2 Files Affected:

(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir (+230-6)
(modified) llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir (+228-4)

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
index 053aede615f86..42600d7d0dd7a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
@@ -3,29 +3,29 @@
 # RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
-name: inttoptr_s
+name: inttoptr_s_p0
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
-    ; CHECK-LABEL: name: inttoptr_s
+    ; CHECK-LABEL: name: inttoptr_s_p0
     ; CHECK: liveins: $sgpr0_sgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
-    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p0) = G_INTTOPTR [[COPY]](s64)
     %0:_(s64) = COPY $sgpr0_sgpr1
-    %1:_(p4) = G_INTTOPTR %0
+    %1:_(p0) = G_INTTOPTR %0
 ...
 
 ---
-name: inttoptr_v
+name: inttoptr_v_p0
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
-    ; CHECK-LABEL: name: inttoptr_v
+    ; CHECK-LABEL: name: inttoptr_v_p0
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
@@ -33,3 +33,227 @@ body: |
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(p0) = G_INTTOPTR %0
 ...
+
+---
+name: inttoptr_s_p1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: inttoptr_s_p1
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p1) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(p1) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: inttoptr_v_p1
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p1) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p1) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p2
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p2) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p2) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p2
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p2) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p2) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p3
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p3) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p3) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p3
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p3) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p3) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: inttoptr_s_p4
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $sgpr0_sgpr1
+    %1:_(p4) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: inttoptr_v_p4
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p4) = G_INTTOPTR [[COPY]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(p4) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p5
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p5) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p5) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p5
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p5) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p5) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: inttoptr_s_p6
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p6) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $sgpr0
+    %1:_(p6) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: inttoptr_v_p6
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p6) = G_INTTOPTR [[COPY]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(p6) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_s_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-LABEL: name: inttoptr_s_p8
+    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:sgpr(p8) = G_INTTOPTR [[COPY]](s128)
+    %0:_(s128) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    %1:_(p8) = G_INTTOPTR %0
+...
+
+---
+name: inttoptr_v_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-LABEL: name: inttoptr_v_p8
+    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:vgpr(p8) = G_INTTOPTR [[COPY]](s128)
+    %0:_(s128) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(p8) = G_INTTOPTR %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
index 2db1a5b1d2ba2..9240c9f6df404 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
@@ -3,13 +3,45 @@
 # RUN: llc -mtriple=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
 
 ---
-name: ptrtoint_s
+name: ptrtoint_s_p0
 legalized: true
 
 body: |
   bb.0:
     liveins: $sgpr0_sgpr1
-    ; CHECK-LABEL: name: ptrtoint_s
+    ; CHECK-LABEL: name: ptrtoint_s_p0
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p0) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s64) = G_PTRTOINT [[COPY]](p0)
+    %0:_(p0) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p0
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: ptrtoint_v_p0
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s64) = G_PTRTOINT [[COPY]](p0)
+    %0:_(p0) = COPY $vgpr0_vgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p1
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: ptrtoint_s_p1
     ; CHECK: liveins: $sgpr0_sgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1
@@ -19,13 +51,13 @@ body: |
 ...
 
 ---
-name: ptrtoint_v
+name: ptrtoint_v_p1
 legalized: true
 
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
-    ; CHECK-LABEL: name: ptrtoint_v
+    ; CHECK-LABEL: name: ptrtoint_v_p1
     ; CHECK: liveins: $vgpr0_vgpr1
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
@@ -33,3 +65,195 @@ body: |
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s64) = G_PTRTOINT %0
 ...
+
+---
+name: ptrtoint_s_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p2
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p2) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p2)
+    %0:_(p2) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p2
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p2
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p2) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p2)
+    %0:_(p2) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p3
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p3)
+    %0:_(p3) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p3
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p3
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p3)
+    %0:_(p3) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK-LABEL: name: ptrtoint_s_p4
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s64) = G_PTRTOINT [[COPY]](p4)
+    %0:_(p4) = COPY $sgpr0_sgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p4
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: ptrtoint_v_p4
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p4) = COPY $vgpr0_vgpr1
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s64) = G_PTRTOINT [[COPY]](p4)
+    %0:_(p4) = COPY $vgpr0_vgpr1
+    %1:_(s64) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p5
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p5) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p5)
+    %0:_(p5) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p5
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p5
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p5) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p5)
+    %0:_(p5) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+    ; CHECK-LABEL: name: ptrtoint_s_p6
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p6) = COPY $sgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s32) = G_PTRTOINT [[COPY]](p6)
+    %0:_(p6) = COPY $sgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p6
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: ptrtoint_v_p6
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p6) = COPY $vgpr0
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s32) = G_PTRTOINT [[COPY]](p6)
+    %0:_(p6) = COPY $vgpr0
+    %1:_(s32) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_s_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-LABEL: name: ptrtoint_s_p8
+    ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p8) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:sgpr(s128) = G_PTRTOINT [[COPY]](p8)
+    %0:_(p8) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
+    %1:_(s128) = G_PTRTOINT %0
+...
+
+---
+name: ptrtoint_v_p8
+legalized: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-LABEL: name: ptrtoint_v_p8
+    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p8) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:vgpr(s128) = G_PTRTOINT [[COPY]](p8)
+    %0:_(p8) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
+    %1:_(s128) = G_PTRTOINT %0
+...

rovka

LGTM

Pierre-vh · 2025-06-19T07:48:09Z

Merge activity

Jun 19, 7:48 AM UTC: A user started a stack merge that includes this pull request via Graphite.
Jun 19, 8:08 AM UTC: Graphite rebased this pull request as part of a merge.
Jun 19, 8:11 AM UTC: Graphite rebased this pull request as part of a merge.
Jun 19, 8:13 AM UTC: @Pierre-vh merged this pull request with Graphite.

Test P0 through P6 + P8 for both S/VGPRs.

This was referenced Jun 3, 2025

[AMDGPU] New RegBankSelect: Handle all 32/64 bit pointer types for B32/B64 rule #142560

Merged

[AMDGPU] New RegBankSelect: Add missing S/VGPR pointer types #142600

Closed

[AMDGPU] New RegBanKSelect: Add S128 types #142601

Merged

This was referenced Jun 3, 2025

[AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 #142602

Merged

[AMDGPU] New RegBankSelect: Add rules for G_PTRTOINT and G_INTTOPTR #142604

Merged

Pierre-vh requested review from arsenm, jayfoad and petar-avramovic June 3, 2025 13:13

Pierre-vh marked this pull request as ready for review June 3, 2025 13:14

llvmbot added backend:AMDGPU llvm:globalisel labels Jun 3, 2025

Pierre-vh force-pushed the users/pierre-vh/newrb-anyptr-types branch from b4da53a to c69258d Compare June 4, 2025 08:09

Pierre-vh force-pushed the users/pierre-vh/test-ptr-int-gisel-rb branch from 6748dc9 to 3a47927 Compare June 4, 2025 08:09

rovka approved these changes Jun 4, 2025

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Pierre-vh force-pushed the users/pierre-vh/newrb-anyptr-types branch 2 times, most recently from 7246639 to e822cdf Compare June 19, 2025 08:03

Base automatically changed from users/pierre-vh/newrb-anyptr-types to main June 19, 2025 08:06

Pierre-vh force-pushed the users/pierre-vh/test-ptr-int-gisel-rb branch from 3a47927 to 8e4ff23 Compare June 19, 2025 08:08

[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT

5163c17

Test P0 through P6 + P8 for both S/VGPRs.

Pierre-vh force-pushed the users/pierre-vh/test-ptr-int-gisel-rb branch from 8e4ff23 to 5163c17 Compare June 19, 2025 08:11

Pierre-vh merged commit 0e1aab1 into main Jun 19, 2025
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Pierre-vh deleted the users/pierre-vh/test-ptr-int-gisel-rb branch June 19, 2025 08:13

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[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT #142603

[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT #142603

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Pierre-vh commented Jun 3, 2025

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Pierre-vh commented Jun 3, 2025 •

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Pierre-vh commented Jun 19, 2025 •

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[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT #142603

[AMDGPU] Improve test coverage for G_INTTOPTR and G_PTRTOINT #142603

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Pierre-vh commented Jun 3, 2025 •

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Pierre-vh commented Jun 19, 2025 •

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