[RISCV] Add documentation in the LangRef on GHC CC

[boomanaiden154]

The GHC CC got added to RISCV in a8dc211 but it never got documented in the LangRef. This adds documentation in the LangRef noting that RISCV is supports the GHC calling convention and notes the specific limitations of the GHC CC on RISCV.

[boomanaiden154]

This is complementary to #72760.

[llvmbot]

@llvm/pr-subscribers-llvm-ir

Author: Aiden Grossman (boomanaiden154)

Changes

The GHC CC got added to RISCV in a8dc211 but it never got documented in the LangRef. This adds documentation in the LangRef noting that RISCV is supports the GHC calling convention and notes the specific limitations of the GHC CC on RISCV.

---

Full diff: https://github.com/llvm/llvm-project/pull/72762.diff

1 Files Affected:

• (modified) llvm/docs/LangRef.rst (+5-2)

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index bc1eab1e0b7a07f..7ba1a1a53d67e25 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -317,13 +317,16 @@ added in the future:
     not be used lightly but only for specific situations such as an
     alternative to the *register pinning* performance technique often
     used when implementing functional programming languages. At the
-    moment only X86 supports this convention and it has the following
-    limitations:
+    moment only X86 and RISCV support this convention. They have the
+    following limitations:
 
     -  On *X86-32* only supports up to 4 bit type parameters. No
        floating-point types are supported.
     -  On *X86-64* only supports up to 10 bit type parameters and 6
        floating-point parameters.
+    -  *RISCV64* only supports up to 11 bit type parameters and 4
+       32-bit floating-point parameters and 4 64-bit floating-point
+       parameters.
 
     This calling convention supports `tail call
     optimization <CodeGenerator.html#tail-call-optimization>`_ but requires

[boomanaiden154]

Bump on this when reviewers have a chance. Thanks!

[boomanaiden154]

Bump on this when reviewers have a chance. Thanks!

[boomanaiden154]

Bump on this when reviewers have a chance. Thanks!

[asb]

If someone else had a chance to re-check the RISC-V specific limitations that would be great, but LGTM from what I can see.

[boomanaiden154]

Thanks for the review! I'll wait a couple days to see if anyone else has comments and then I'll land it at that point.