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[SelectionDAG] Add space-optimized forms of OPC_EmitRegister #73291

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Merged
merged 1 commit into from
Dec 19, 2023

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The followed byte of OPC_EmitRegister is a MVT type, which is
usually i32 or i64.

We add OPC_EmitRegisterI32 and OPC_EmitRegisterI64 so that we
can reduce one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 10K.

@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Nov 24, 2023
@wangpc-pp wangpc-pp requested a review from ilovepi November 24, 2023 07:11
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llvmbot commented Nov 24, 2023

@llvm/pr-subscribers-llvm-selectiondag

Author: Wang Pengcheng (wangpc-pp)

Changes

The followed byte of OPC_EmitRegister is a MVT type, which is
usually i32 or i64.

We add OPC_EmitRegisterI32 and OPC_EmitRegisterI64 so that we
can reduce one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 10K.


Full diff: https://github.com/llvm/llvm-project/pull/73291.diff

3 Files Affected:

  • (modified) llvm/include/llvm/CodeGen/SelectionDAGISel.h (+2)
  • (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+15-3)
  • (modified) llvm/utils/TableGen/DAGISelMatcherEmitter.cpp (+15-3)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index ffeb4959ba7d076..e05a3e903c28048 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -161,6 +161,8 @@ class SelectionDAGISel : public MachineFunctionPass {
     OPC_EmitInteger,
     OPC_EmitStringInteger,
     OPC_EmitRegister,
+    OPC_EmitRegisterI32,
+    OPC_EmitRegisterI64,
     OPC_EmitRegister2,
     OPC_EmitConvertToTarget,
     OPC_EmitMergeInputChains,
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7d9bebdca127224..a5005d74faffeb7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3465,9 +3465,21 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
                                                         VT), nullptr));
       continue;
     }
-    case OPC_EmitRegister: {
-      MVT::SimpleValueType VT =
-        (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
+    case OPC_EmitRegister:
+    case OPC_EmitRegisterI32:
+    case OPC_EmitRegisterI64: {
+      MVT::SimpleValueType VT;
+      switch (Opcode) {
+      case OPC_EmitRegisterI32:
+        VT = MVT::i32;
+        break;
+      case OPC_EmitRegisterI64:
+        VT = MVT::i64;
+        break;
+      default:
+        VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
+        break;
+      }
       unsigned RegNo = MatcherTable[MatcherIndex++];
       RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
                               CurDAG->getRegister(RegNo, VT), nullptr));
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 4a11991036efc11..4f1f4b2512a626c 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -687,14 +687,26 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
   case Matcher::EmitRegister: {
     const EmitRegisterMatcher *Matcher = cast<EmitRegisterMatcher>(N);
     const CodeGenRegister *Reg = Matcher->getReg();
+    MVT::SimpleValueType VT = Matcher->getVT();
     // If the enum value of the register is larger than one byte can handle,
     // use EmitRegister2.
     if (Reg && Reg->EnumValue > 255) {
-      OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", ";
+      OS << "OPC_EmitRegister2, " << getEnumName(VT) << ", ";
       OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
       return 4;
     } else {
-      OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", ";
+      unsigned OpBytes;
+      switch (VT) {
+      case MVT::i32:
+      case MVT::i64:
+        OpBytes = 1;
+        OS << "OPC_EmitRegisterI" << MVT(VT).getScalarSizeInBits() << ", ";
+        break;
+      default:
+        OpBytes = 2;
+        OS << "OPC_EmitRegister, " << getEnumName(VT) << ", ";
+        break;
+      }
       if (Reg) {
         OS << getQualifiedName(Reg->TheDef) << ",\n";
       } else {
@@ -703,7 +715,7 @@ EmitMatcher(const Matcher *N, const unsigned Indent, unsigned CurrentIdx,
           OS << "/*zero_reg*/";
         OS << ",\n";
       }
-      return 3;
+      return OpBytes + 1;
     }
   }
 

@wangpc-pp wangpc-pp requested review from asb, RKSimon and topperc November 24, 2023 07:12
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github-actions bot commented Nov 24, 2023

✅ With the latest revision this PR passed the C/C++ code formatter.

@wangpc-pp wangpc-pp force-pushed the main-matcher-table-emit-register branch from 4929a5d to a4d0c6f Compare November 24, 2023 07:14
@wangpc-pp wangpc-pp requested a review from jrtc27 November 27, 2023 03:19
@wangpc-pp wangpc-pp requested a review from arsenm November 28, 2023 11:46
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Ping.

@wangpc-pp wangpc-pp force-pushed the main-matcher-table-emit-register branch from a4d0c6f to 9216f54 Compare December 12, 2023 09:23
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Ping.

The followed byte of `OPC_EmitRegister` is a MVT type, which is
usually i32 or i64.

We add `OPC_EmitRegisterI32` and `OPC_EmitRegisterI64` so that we
can reduce one byte.

Overall this reduces the llc binary size with all in-tree targets by
about 10K.
@wangpc-pp wangpc-pp force-pushed the main-matcher-table-emit-register branch from 9216f54 to b3a726e Compare December 19, 2023 09:31
@wangpc-pp wangpc-pp merged commit 9348d43 into llvm:main Dec 19, 2023
@wangpc-pp wangpc-pp deleted the main-matcher-table-emit-register branch December 19, 2023 09:32
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4 participants