[RISCV] Add Ssqosid support to -march. #80747

topperc · 2024-02-05T21:47:18Z

No description provided.

llvmbot · 2024-02-05T21:47:47Z

@llvm/pr-subscribers-llvm-support
@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-mc

Author: Craig Topper (topperc)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/80747.diff

8 Files Affected:

(modified) clang/test/Preprocessor/riscv-target-features.c (+9)
(modified) llvm/docs/RISCVUsage.rst (+3)
(modified) llvm/docs/ReleaseNotes.rst (+1)
(modified) llvm/lib/Support/RISCVISAInfo.cpp (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+3)
(modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1)

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index add96c0046cc7..e65c8cd43b245 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -163,6 +163,7 @@
 // CHECK-NOT: __riscv_smnpm{{.*$}}
 // CHECK-NOT: __riscv_ssnpm{{.*$}}
 // CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_ssqosid{{.*$}}
 // CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
@@ -1612,6 +1613,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
 // CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_ssqosid1p0 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index c9e99c9b98e37..43c6c3f116c5d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -246,6 +246,9 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
   LLVM implements the `v0.8.1 draft specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`
 
+``experimental-ssqosid``
+  LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
+
 ``experimental-zabha``
   LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`_.
 
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6ac83961d7cf0..05d8eea3add41 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -102,6 +102,7 @@ Changes to the RISC-V Backend
   names in the RISC-V profiles specification are now recognised.
 * Codegen support was added for the Zimop (May-Be-Operations) extension.
 * The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported.
+* The experimental Ssqosid extension is supported.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 6fe8eb62e2804..d028302b8c4d9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -215,6 +215,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"smnpm", {0, 8}},
     {"ssnpm", {0, 8}},
     {"sspm", {0, 8}},
+    {"ssqosid", {1, 0}},
     {"supm", {0, 8}},
 
     {"zaamo", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 03ccda4561ed8..03e0980402107 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -828,6 +828,10 @@ def FeatureStdExtSstc
     : SubtargetFeature<"sstc", "HasStdExtSstc", "true",
                        "'Sstc' (Supervisor-mode timer interrupts)", []>;
 
+def FeaturesSsqosid
+    : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true",
+                       "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>;
+
 def FeatureStdExtShtvala
     : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
                        "'Shtvala' (htval provides all needed values)", []>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 088cc0b90a05a..13635a94d6411 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -121,6 +121,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -249,6 +250,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
 
 ; CHECK: .attribute 4, 16
 
@@ -372,6 +374,7 @@
 ; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8"
 ; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8"
 ; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
+; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -499,6 +502,7 @@
 ; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8"
 ; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8"
 ; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
+; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 34b7ee52da320..873037ea0caa2 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -321,6 +321,9 @@
 .attribute arch, "rv32i_sscounterenw1p0"
 # CHECK: attribute      5, "rv32i2p1_sscounterenw1p0"
 
+.attribute arch, "rv32i_ssqosid1p0"
+# CHECK: attribute      5, "rv32i2p1_ssqosid1p0"
+
 .attribute arch, "rv32i_ssstateen1p0"
 # CHECK: attribute      5, "rv32i2p1_ssstateen1p0"
 
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index ac6066ebdfb94..df4c7f7de8a3d 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -885,6 +885,7 @@ Experimental extensions
     smnpm               0.8
     ssnpm               0.8
     sspm                0.8
+    ssqosid             1.0
     supm                0.8
 
 Use -march to specify the target's extension.

llvmbot · 2024-02-05T21:47:47Z

@llvm/pr-subscribers-clang

Author: Craig Topper (topperc)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/80747.diff

8 Files Affected:

(modified) clang/test/Preprocessor/riscv-target-features.c (+9)
(modified) llvm/docs/RISCVUsage.rst (+3)
(modified) llvm/docs/ReleaseNotes.rst (+1)
(modified) llvm/lib/Support/RISCVISAInfo.cpp (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4)
(modified) llvm/test/CodeGen/RISCV/attributes.ll (+4)
(modified) llvm/test/MC/RISCV/attribute-arch.s (+3)
(modified) llvm/unittests/Support/RISCVISAInfoTest.cpp (+1)

diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
index add96c0046cc7..e65c8cd43b245 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -163,6 +163,7 @@
 // CHECK-NOT: __riscv_smnpm{{.*$}}
 // CHECK-NOT: __riscv_ssnpm{{.*$}}
 // CHECK-NOT: __riscv_sspm{{.*$}}
+// CHECK-NOT: __riscv_ssqosid{{.*$}}
 // CHECK-NOT: __riscv_supm{{.*$}}
 // CHECK-NOT: __riscv_zaamo {{.*$}}
 // CHECK-NOT: __riscv_zacas {{.*$}}
@@ -1612,6 +1613,14 @@
 // RUN:   -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
 // CHECK-SUPM-EXT: __riscv_supm 8000{{$}}
 
+// RUN: %clang --target=riscv32 -menable-experimental-extensions \
+// RUN:   -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_ssqosid1p0 -E -dM %s -menable-experimental-extensions \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}
+
 // Misaligned
 
 // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index c9e99c9b98e37..43c6c3f116c5d 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -246,6 +246,9 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
   LLVM implements the `v0.8.1 draft specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`
 
+``experimental-ssqosid``
+  LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
+
 ``experimental-zabha``
   LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`_.
 
diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 6ac83961d7cf0..05d8eea3add41 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -102,6 +102,7 @@ Changes to the RISC-V Backend
   names in the RISC-V profiles specification are now recognised.
 * Codegen support was added for the Zimop (May-Be-Operations) extension.
 * The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported.
+* The experimental Ssqosid extension is supported.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index 6fe8eb62e2804..d028302b8c4d9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -215,6 +215,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"smnpm", {0, 8}},
     {"ssnpm", {0, 8}},
     {"sspm", {0, 8}},
+    {"ssqosid", {1, 0}},
     {"supm", {0, 8}},
 
     {"zaamo", {0, 2}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 03ccda4561ed8..03e0980402107 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -828,6 +828,10 @@ def FeatureStdExtSstc
     : SubtargetFeature<"sstc", "HasStdExtSstc", "true",
                        "'Sstc' (Supervisor-mode timer interrupts)", []>;
 
+def FeaturesSsqosid
+    : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true",
+                       "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>;
+
 def FeatureStdExtShtvala
     : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
                        "'Shtvala' (htval provides all needed values)", []>;
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 088cc0b90a05a..13635a94d6411 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -121,6 +121,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -249,6 +250,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
 
 ; CHECK: .attribute 4, 16
 
@@ -372,6 +374,7 @@
 ; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8"
 ; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8"
 ; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
+; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -499,6 +502,7 @@
 ; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8"
 ; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8"
 ; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
+; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index 34b7ee52da320..873037ea0caa2 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -321,6 +321,9 @@
 .attribute arch, "rv32i_sscounterenw1p0"
 # CHECK: attribute      5, "rv32i2p1_sscounterenw1p0"
 
+.attribute arch, "rv32i_ssqosid1p0"
+# CHECK: attribute      5, "rv32i2p1_ssqosid1p0"
+
 .attribute arch, "rv32i_ssstateen1p0"
 # CHECK: attribute      5, "rv32i2p1_ssstateen1p0"
 
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index ac6066ebdfb94..df4c7f7de8a3d 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -885,6 +885,7 @@ Experimental extensions
     smnpm               0.8
     ssnpm               0.8
     sspm                0.8
+    ssqosid             1.0
     supm                0.8
 
 Use -march to specify the target's extension.

wangpc-pp · 2024-02-06T03:46:08Z

clang/test/Preprocessor/riscv-target-features.c

+// RUN:   -march=rv32i_ssqosid1p0 -E -dM %s \
+// RUN:   -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
+// RUN: %clang --target=riscv64 \
+// RUN:   -march=rv64i_ssqosid1p0 -E -dM %s -menable-experimental-extensions \


Why is -menable-experimental-extensions here?

It's not ratified yet right?

It is required for clang when using experimental RISC-V extensions.

def menable_experimental_extensions : Flag<["-"], "menable-experimental-extensions">, Group<m_Group>,
HelpText<"Enable use of experimental RISC-V extensions.">;

Oh sorry, I meant why -menable-experimental-extensions is in line 1620, not line 1619.

Because I copied it from supm which has the same issue.

asb

LGTM.

[RISCV] Add Ssqosid support to -march.

a92d114

topperc requested review from asb, preames, lukel97 and wangpc-pp February 5, 2024 21:47

llvmbot added clang Clang issues not falling into any other category backend:RISC-V mc Machine (object) code llvm:support labels Feb 5, 2024

wangpc-pp reviewed Feb 6, 2024

View reviewed changes

asb approved these changes Feb 6, 2024

View reviewed changes

fixup! Address review comment

f94cb9d

topperc merged commit 2faeea3 into llvm:main Feb 6, 2024

topperc deleted the pr/ssqosid branch February 6, 2024 18:06

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[RISCV] Add Ssqosid support to -march. #80747

[RISCV] Add Ssqosid support to -march. #80747

Uh oh!

topperc commented Feb 5, 2024

Uh oh!

llvmbot commented Feb 5, 2024 •

edited

Loading

Uh oh!

llvmbot commented Feb 5, 2024

Uh oh!

wangpc-pp Feb 6, 2024

Uh oh!

topperc Feb 6, 2024

Uh oh!

dtcxzyw Feb 6, 2024

Uh oh!

wangpc-pp Feb 6, 2024

Uh oh!

topperc Feb 6, 2024

Uh oh!

asb left a comment

Uh oh!

Uh oh!

[RISCV] Add Ssqosid support to -march. #80747

[RISCV] Add Ssqosid support to -march. #80747

Uh oh!

Conversation

topperc commented Feb 5, 2024

Uh oh!

llvmbot commented Feb 5, 2024 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

llvmbot commented Feb 5, 2024

Uh oh!

wangpc-pp Feb 6, 2024

Choose a reason for hiding this comment

Uh oh!

topperc Feb 6, 2024

Choose a reason for hiding this comment

Uh oh!

dtcxzyw Feb 6, 2024

Choose a reason for hiding this comment

Uh oh!

wangpc-pp Feb 6, 2024

Choose a reason for hiding this comment

Uh oh!

topperc Feb 6, 2024

Choose a reason for hiding this comment

Uh oh!

asb left a comment

Choose a reason for hiding this comment

Uh oh!

Uh oh!

llvmbot commented Feb 5, 2024 •

edited

Loading