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[RISCV] Add Ssqosid support to -march. #80747

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Merged
merged 2 commits into from
Feb 6, 2024
Merged

[RISCV] Add Ssqosid support to -march. #80747

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a92d114
[RISCV] Add Ssqosid support to -march.
topperc Feb 5, 2024
f94cb9d
fixup! Address review comment
topperc Feb 6, 2024
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17 changes: 13 additions & 4 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -163,6 +163,7 @@
// CHECK-NOT: __riscv_smnpm{{.*$}}
// CHECK-NOT: __riscv_ssnpm{{.*$}}
// CHECK-NOT: __riscv_sspm{{.*$}}
// CHECK-NOT: __riscv_ssqosid{{.*$}}
// CHECK-NOT: __riscv_supm{{.*$}}
// CHECK-NOT: __riscv_zaamo {{.*$}}
// CHECK-NOT: __riscv_zacas {{.*$}}
Expand Down Expand Up @@ -1599,19 +1600,27 @@
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_sspm0p8 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_sspm0p8 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
// CHECK-SSPM-EXT: __riscv_sspm 8000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_supm0p8 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_supm0p8 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 8000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}

// Misaligned

// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \
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3 changes: 3 additions & 0 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -246,6 +246,9 @@ The primary goal of experimental support is to assist in the process of ratifica
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
LLVM implements the `v0.8.1 draft specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`

``experimental-ssqosid``
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.

``experimental-zabha``
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`_.

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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -102,6 +102,7 @@ Changes to the RISC-V Backend
names in the RISC-V profiles specification are now recognised.
* Codegen support was added for the Zimop (May-Be-Operations) extension.
* The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported.
* The experimental Ssqosid extension is supported.

Changes to the WebAssembly Backend
----------------------------------
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1 change: 1 addition & 0 deletions llvm/lib/Support/RISCVISAInfo.cpp
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Expand Up @@ -215,6 +215,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"smnpm", {0, 8}},
{"ssnpm", {0, 8}},
{"sspm", {0, 8}},
{"ssqosid", {1, 0}},
{"supm", {0, 8}},

{"zaamo", {0, 2}},
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -828,6 +828,10 @@ def FeatureStdExtSstc
: SubtargetFeature<"sstc", "HasStdExtSstc", "true",
"'Sstc' (Supervisor-mode timer interrupts)", []>;

def FeaturesSsqosid
: SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true",
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>;

def FeatureStdExtShtvala
: SubtargetFeature<"shtvala", "HasStdExtShtvala", "true",
"'Shtvala' (htval provides all needed values)", []>;
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4 changes: 4 additions & 0 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -121,6 +121,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s

; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
Expand Down Expand Up @@ -249,6 +250,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s

; CHECK: .attribute 4, 16

Expand Down Expand Up @@ -372,6 +374,7 @@
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8"
; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8"
; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"

; RV64M: .attribute 5, "rv64i2p1_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
Expand Down Expand Up @@ -499,6 +502,7 @@
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8"
; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8"
; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"

define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
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3 changes: 3 additions & 0 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -321,6 +321,9 @@
.attribute arch, "rv32i_sscounterenw1p0"
# CHECK: attribute 5, "rv32i2p1_sscounterenw1p0"

.attribute arch, "rv32i_ssqosid1p0"
# CHECK: attribute 5, "rv32i2p1_ssqosid1p0"

.attribute arch, "rv32i_ssstateen1p0"
# CHECK: attribute 5, "rv32i2p1_ssstateen1p0"

Expand Down
1 change: 1 addition & 0 deletions llvm/unittests/Support/RISCVISAInfoTest.cpp
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Expand Up @@ -885,6 +885,7 @@ Experimental extensions
smnpm 0.8
ssnpm 0.8
sspm 0.8
ssqosid 1.0
supm 0.8

Use -march to specify the target's extension.
Expand Down