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[clang][RISCV] Reorder sema check for RVV type #83553

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Merged
merged 3 commits into from
Mar 6, 2024
Merged

[clang][RISCV] Reorder sema check for RVV type #83553

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8ad3a88
[clang][RISCV] Reorder sema check for RVV type
4vtomat Mar 1, 2024
779aeba
fixup! [clang][RISCV] Reorder sema check for RVV type
4vtomat Mar 1, 2024
ee33c7d
fixup! [clang][RISCV] Reorder sema check for RVV type
4vtomat Mar 2, 2024
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11 changes: 6 additions & 5 deletions clang/lib/Sema/SemaChecking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6332,10 +6332,14 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();

if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
!TI.hasFeature("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
!TI.hasFeature("zve64x"))
else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||
MinElts == 1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
!TI.hasFeature("zvfhmin"))
Expand All @@ -6347,9 +6351,6 @@ void Sema::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
!TI.hasFeature("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
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3 changes: 1 addition & 2 deletions clang/test/Sema/riscv-vector-float64-check.c
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@@ -1,5 +1,4 @@
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +zve64f -target-feature +zfh \
// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: riscv-registered-target
#include <riscv_vector.h>
Expand Down