[RISCV] Mark all registers marked isConstant as reserved

[francisvm]

This makes use of the information from TableGen instead of duplicating it in the code.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

Author: Francis Visoiu Mistrih (francisvm)

Changes

This makes use of the information from TableGen instead of duplicating it in the code.

---

Full diff: https://github.com/llvm/llvm-project/pull/96002.diff

1 Files Affected:

• (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+4-3)

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index caa5dbc15f8bd..349433a29a36b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -104,14 +104,16 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
-  // Mark any registers requested to be reserved as such
   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
+    // Mark any registers requested to be reserved as such
     if (Subtarget.isRegisterReservedByUser(Reg))
       markSuperRegs(Reserved, Reg);
+    // Mark all the registers defined as constant in TableGen as reserved.
+    if (isConstantPhysReg(Reg))
+      markSuperRegs(Reserved, Reg);
   }
 
   // Use markSuperRegs to ensure any register aliases are also reserved
-  markSuperRegs(Reserved, RISCV::X0); // zero
   markSuperRegs(Reserved, RISCV::X2); // sp
   markSuperRegs(Reserved, RISCV::X3); // gp
   markSuperRegs(Reserved, RISCV::X4); // tp
@@ -136,7 +138,6 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, RISCV::VTYPE);
   markSuperRegs(Reserved, RISCV::VXSAT);
   markSuperRegs(Reserved, RISCV::VXRM);
-  markSuperRegs(Reserved, RISCV::VLENB); // vlenb (constant)
 
   // Floating point environment registers.
   markSuperRegs(Reserved, RISCV::FRM);

[wangpc-pp]

LGTM.

[topperc]

I find it odd that this loop was looping over more than just the GPRs originally since those are the only ones that can be reserved. We could maybe save some compile time by not checking every register, but this patch now requires us to check every register.

[wangpc-pp]

Good point!
So I think we should iterate through all GPRs explicitly here.

[francisvm]

I went with iterating from RISCV::NoRegister to RISCV::NUM_TARGET_REGS, with a GPR check before calling Subtarget.isRegisterReservedByUser.

[topperc]

To be honest, I like your first patch better. As long as RISCVSubtarget uses std::bitset<RISCV::NUM_TARGET_REGS> to track reserved registers, we should continue iterating all of the registers.

[francisvm]

Yeah I kind of agree. I reverted it back to the initial patch. I don't think calling isRegisterReservedByUser with non-GPRs is an issue.

[topperc]

Maybe isRegisterReservedByUser should be replaced by isGPRRegisterReservedByUser. My main point was that as the number of registers increases with new extensions, this loop gets more and more iterations, making the function slower even if the new registers don't need to be reserved.

[topperc]

LGTM