Add extended mnemonics #97571
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Add extended mnemonics #97571
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This is accomplished by two additional instruction formats, representing conditional branch instructions whose condition is never true.
This adds aliases JC, JCTH, LFI, LLGFI and LLGHI
This necessitates a new InstructionFormat (UnaryRRFa). The instructions are not made available for the disassembler because distinguishing their encoding from encodings of other instructions (NORK and NOGRK) requires a check on the register choice (R2 == R3) that, to my knowledge, the disassembler is currently not capable of.
…n format Also add two extended mnemonics that use this feature, RISBGZ and RISBGNZ. T and Z bit handling are provided by extending the RIE-f format with two optional `bits<8>` parameters that OR their content onto the I3 and I4 fields. Setting these to `0x80` ensures that the highest bit of I3 or I4 will be set, thus setting the T or Z bit, respectively.
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@llvm/pr-subscribers-lld @llvm/pr-subscribers-mc Author: Dominik Steenken (dominik-steenken) ChangesThis PR adds a number of thus-far missing extended mnemonics to the assembler and disassembler for SystemZ. The following mnemonics have been added and are supported for the assembler and disassembler:
The following mnemonics have been added and are supported for the assembler only:
Patch is 38.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/97571.diff 13 Files Affected:
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 3dba33b66bf4f..f2eb331f2426d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -363,7 +363,7 @@ class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = op{7-0};
}
-class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
@@ -377,8 +377,22 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
- let Inst{31-24} = I3;
- let Inst{23-16} = I4;
+ let Inst{31} = !if(I3Or{7}, 1, I3{7});
+ let Inst{30} = !if(I3Or{6}, 1, I3{6});
+ let Inst{29} = !if(I3Or{5}, 1, I3{5});
+ let Inst{28} = !if(I3Or{4}, 1, I3{4});
+ let Inst{27} = !if(I3Or{3}, 1, I3{3});
+ let Inst{26} = !if(I3Or{2}, 1, I3{2});
+ let Inst{25} = !if(I3Or{1}, 1, I3{1});
+ let Inst{24} = !if(I3Or{0}, 1, I3{0});
+ let Inst{23} = !if(I4Or{7}, 1, I4{7});
+ let Inst{22} = !if(I4Or{6}, 1, I4{6});
+ let Inst{21} = !if(I4Or{5}, 1, I4{5});
+ let Inst{20} = !if(I4Or{4}, 1, I4{4});
+ let Inst{19} = !if(I4Or{3}, 1, I4{3});
+ let Inst{18} = !if(I4Or{2}, 1, I4{2});
+ let Inst{17} = !if(I4Or{1}, 1, I4{1});
+ let Inst{16} = !if(I4Or{0}, 1, I4{0});
let Inst{15-8} = I5;
let Inst{7-0} = op{7-0};
}
@@ -2349,6 +2363,12 @@ class AsmCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
mnemonic#"\t$R1, $R2", []>;
+class NeverCondBranchRR<string mnemonic, bits<8> opcode>
+ : InstRR<opcode, (outs), (ins GR64:$R2),
+ mnemonic#"\t$R2", []> {
+ let R1 = 0;
+}
+
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
SDPatternOperator operator = null_frag>
: InstRR<opcode, (outs), (ins ADDR64:$R2),
@@ -2370,6 +2390,13 @@ class AsmCondBranchRX<string mnemonic, bits<8> opcode>
(ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
+class NeverCondBranchRX<string mnemonic, bits<8> opcode>
+ : InstRXb<opcode, (outs),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ mnemonic#"\t$XBD2", []> {
+ let M1 = 0;
+}
+
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
@@ -3439,6 +3466,19 @@ class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpType = "reg";
}
+
+class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
+ mnemonic#"\t$R1, $R2",
+ [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> {
+ let R3 = R2;
+ let M4 = 0;
+ let OpKey = mnemonic#cls1;
+ let OpType = "reg";
+}
+
+
multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
SDPatternOperator operator, RegisterOperand cls1,
RegisterOperand cls2> {
@@ -4999,11 +5039,22 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
}
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
- RegisterOperand cls2>
+ RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
imm32zx8:$I5),
- mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
+ mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
+class FixedRotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+ RegisterOperand cls2, bits<8> I3_in, bits<8> I4_in, bits<8> I5_in = 0>
+ : InstRIEf<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
+ mnemonic#"\t$R1, $R2", []> {
+ let I3 = I3_in;
+ let I4 = I4_in;
+ let I5 = I5_in;
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 7c6ab3f9b1ab5..898b80e3a7a3d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -111,11 +111,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// NOPs. These are again variants of the conditional branches, with the
// condition mask set to "never". NOP_bare can't be an InstAlias since it
// would need R0D hard coded which is not part of ADDR64BitRegClass.
-def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
+def NOP : NeverCondBranchRX<"nop", 0x47>;
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
-def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
-def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
+def NOPR : NeverCondBranchRR<"nopr", 0x07>;
+def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>;
+// def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
+// let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
+// def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
+// def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
+// def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
// An alias of BRC 0, label
def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
@@ -464,6 +469,8 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
}
+def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>;
+def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>;
// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
@@ -973,6 +980,7 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
}
+def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>;
def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
@@ -1372,6 +1380,10 @@ let Predicates = [FeatureMiscellaneousExtensions3],
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>;
def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>;
+ let isAsmParserOnly = 1 in {
+ def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>;
+ def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>;
+ }
}
// NXOR.
@@ -1526,13 +1538,17 @@ def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
let Defs = [CC] in {
let isCodeGenOnly = 1 in
def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
- let CCValues = 0xE, CompareZeroCCMask = 0xE in
+ let CCValues = 0xE, CompareZeroCCMask = 0xE in {
def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
+ def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;
+ }
}
// On zEC12 we have a variant of RISBG that does not set CC.
-let Predicates = [FeatureMiscellaneousExtensions] in
+let Predicates = [FeatureMiscellaneousExtensions] in {
def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
+ def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;
+}
// Forms of RISBG that only affect one word of the destination register.
// They do not set CC.
@@ -1550,9 +1566,22 @@ let Predicates = [FeatureHighWord] in {
// bits of the first operand. The CC result only describes the selected bits,
// so isn't useful for a full comparison against zero.
let Defs = [CC] in {
- def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
- def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
- def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
+ def NHHR : FixedRotateSelectRIEf<"nhhr", 0xEC54, GR64, GR64, 0, 31>;
+ def NHLR : FixedRotateSelectRIEf<"nhlr", 0xEC54, GR64, GR64, 0, 31, 32>;
+ def NLHR : FixedRotateSelectRIEf<"nlhr", 0xEC54, GR64, GR64, 32, 63, 32>;
+ def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
+ def OHHR : FixedRotateSelectRIEf<"ohhr", 0xEC56, GR64, GR64, 0, 31>;
+ def OHLR : FixedRotateSelectRIEf<"ohlr", 0xEC56, GR64, GR64, 0, 31, 32>;
+ def OLHR : FixedRotateSelectRIEf<"olhr", 0xEC56, GR64, GR64, 32, 63, 32>;
+ def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ def XHHR : FixedRotateSelectRIEf<"xhhr", 0xEC57, GR64, GR64, 0, 31>;
+ def XHLR : FixedRotateSelectRIEf<"xhlr", 0xEC57, GR64, GR64, 0, 31, 32>;
+ def XLHR : FixedRotateSelectRIEf<"xlhr", 0xEC57, GR64, GR64, 32, 63, 32>;
+ // 128 on I3 sets the T bit for the instruction
+ def RNSBGT : RotateSelectRIEf<"rnsbgt", 0xEC54, GR64, GR64, 128>;
+ def ROSBGT : RotateSelectRIEf<"rosbgt", 0xEC56, GR64, GR64, 128>;
+ def RXSBGT : RotateSelectRIEf<"rxsbgt", 0xEC57, GR64, GR64, 128>;
}
//===----------------------------------------------------------------------===//
@@ -2330,6 +2359,8 @@ defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>;
def JCT : MnemonicAlias<"jct", "brct">;
def JCTG : MnemonicAlias<"jctg", "brctg">;
+def JC : MnemonicAlias<"jc", "brc">;
+def JCTH : MnemonicAlias<"jcth", "brcth">;
def JAS : MnemonicAlias<"jas", "bras">;
def JASL : MnemonicAlias<"jasl", "brasl">;
def JXH : MnemonicAlias<"jxh", "brxh">;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index 9ce1a0d06b5af..3e87b2ed7ae9c 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -506,13 +506,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1553,5 +1554,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index 120d4a457ee39..323262b831e3a 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -516,13 +516,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1643,5 +1644,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index acba3a1fd9919..3a1eec594590e 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
//===----------------------------------------------------------------------===//
@@ -530,13 +531,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1689,5 +1691,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index dd82b2b9b71e7..0a56fd78fb09b 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
//===----------------------------------------------------------------------===//
@@ -530,13 +531,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1722,5 +1724,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 226db9d4272f9..64bd642e0d2f8 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -469,13 +469,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1235,5 +1236,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index f5ecdb1f43800..a8dfe3b0391c6 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -480,13 +480,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1280,5 +1281,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===-------------------------------------...
[truncated]
|
|
@llvm/pr-subscribers-backend-systemz Author: Dominik Steenken (dominik-steenken) ChangesThis PR adds a number of thus-far missing extended mnemonics to the assembler and disassembler for SystemZ. The following mnemonics have been added and are supported for the assembler and disassembler:
The following mnemonics have been added and are supported for the assembler only:
Patch is 38.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/97571.diff 13 Files Affected:
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 3dba33b66bf4f..f2eb331f2426d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -363,7 +363,7 @@ class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = op{7-0};
}
-class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
@@ -377,8 +377,22 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
- let Inst{31-24} = I3;
- let Inst{23-16} = I4;
+ let Inst{31} = !if(I3Or{7}, 1, I3{7});
+ let Inst{30} = !if(I3Or{6}, 1, I3{6});
+ let Inst{29} = !if(I3Or{5}, 1, I3{5});
+ let Inst{28} = !if(I3Or{4}, 1, I3{4});
+ let Inst{27} = !if(I3Or{3}, 1, I3{3});
+ let Inst{26} = !if(I3Or{2}, 1, I3{2});
+ let Inst{25} = !if(I3Or{1}, 1, I3{1});
+ let Inst{24} = !if(I3Or{0}, 1, I3{0});
+ let Inst{23} = !if(I4Or{7}, 1, I4{7});
+ let Inst{22} = !if(I4Or{6}, 1, I4{6});
+ let Inst{21} = !if(I4Or{5}, 1, I4{5});
+ let Inst{20} = !if(I4Or{4}, 1, I4{4});
+ let Inst{19} = !if(I4Or{3}, 1, I4{3});
+ let Inst{18} = !if(I4Or{2}, 1, I4{2});
+ let Inst{17} = !if(I4Or{1}, 1, I4{1});
+ let Inst{16} = !if(I4Or{0}, 1, I4{0});
let Inst{15-8} = I5;
let Inst{7-0} = op{7-0};
}
@@ -2349,6 +2363,12 @@ class AsmCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
mnemonic#"\t$R1, $R2", []>;
+class NeverCondBranchRR<string mnemonic, bits<8> opcode>
+ : InstRR<opcode, (outs), (ins GR64:$R2),
+ mnemonic#"\t$R2", []> {
+ let R1 = 0;
+}
+
class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
SDPatternOperator operator = null_frag>
: InstRR<opcode, (outs), (ins ADDR64:$R2),
@@ -2370,6 +2390,13 @@ class AsmCondBranchRX<string mnemonic, bits<8> opcode>
(ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []>;
+class NeverCondBranchRX<string mnemonic, bits<8> opcode>
+ : InstRXb<opcode, (outs),
+ (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
+ mnemonic#"\t$XBD2", []> {
+ let M1 = 0;
+}
+
class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
@@ -3439,6 +3466,19 @@ class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpType = "reg";
}
+
+class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
+ RegisterOperand cls1, RegisterOperand cls2>
+ : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
+ mnemonic#"\t$R1, $R2",
+ [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> {
+ let R3 = R2;
+ let M4 = 0;
+ let OpKey = mnemonic#cls1;
+ let OpType = "reg";
+}
+
+
multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
SDPatternOperator operator, RegisterOperand cls1,
RegisterOperand cls2> {
@@ -4999,11 +5039,22 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
}
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
- RegisterOperand cls2>
+ RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
imm32zx8:$I5),
- mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
+ mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> {
+ let Constraints = "$R1 = $R1src";
+ let DisableEncoding = "$R1src";
+}
+
+class FixedRotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
+ RegisterOperand cls2, bits<8> I3_in, bits<8> I4_in, bits<8> I5_in = 0>
+ : InstRIEf<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
+ mnemonic#"\t$R1, $R2", []> {
+ let I3 = I3_in;
+ let I4 = I4_in;
+ let I5 = I5_in;
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 7c6ab3f9b1ab5..898b80e3a7a3d 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -111,11 +111,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// NOPs. These are again variants of the conditional branches, with the
// condition mask set to "never". NOP_bare can't be an InstAlias since it
// would need R0D hard coded which is not part of ADDR64BitRegClass.
-def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
+def NOP : NeverCondBranchRX<"nop", 0x47>;
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
-def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
-def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
+def NOPR : NeverCondBranchRR<"nopr", 0x07>;
+def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>;
+// def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
+// let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
+// def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
+// def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
+// def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
// An alias of BRC 0, label
def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
@@ -464,6 +469,8 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
}
+def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>;
+def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>;
// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
@@ -973,6 +980,7 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
}
+def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>;
def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
@@ -1372,6 +1380,10 @@ let Predicates = [FeatureMiscellaneousExtensions3],
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>;
def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>;
+ let isAsmParserOnly = 1 in {
+ def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>;
+ def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>;
+ }
}
// NXOR.
@@ -1526,13 +1538,17 @@ def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
let Defs = [CC] in {
let isCodeGenOnly = 1 in
def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
- let CCValues = 0xE, CompareZeroCCMask = 0xE in
+ let CCValues = 0xE, CompareZeroCCMask = 0xE in {
def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
+ def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;
+ }
}
// On zEC12 we have a variant of RISBG that does not set CC.
-let Predicates = [FeatureMiscellaneousExtensions] in
+let Predicates = [FeatureMiscellaneousExtensions] in {
def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
+ def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;
+}
// Forms of RISBG that only affect one word of the destination register.
// They do not set CC.
@@ -1550,9 +1566,22 @@ let Predicates = [FeatureHighWord] in {
// bits of the first operand. The CC result only describes the selected bits,
// so isn't useful for a full comparison against zero.
let Defs = [CC] in {
- def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
- def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
- def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
+ def NHHR : FixedRotateSelectRIEf<"nhhr", 0xEC54, GR64, GR64, 0, 31>;
+ def NHLR : FixedRotateSelectRIEf<"nhlr", 0xEC54, GR64, GR64, 0, 31, 32>;
+ def NLHR : FixedRotateSelectRIEf<"nlhr", 0xEC54, GR64, GR64, 32, 63, 32>;
+ def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
+ def OHHR : FixedRotateSelectRIEf<"ohhr", 0xEC56, GR64, GR64, 0, 31>;
+ def OHLR : FixedRotateSelectRIEf<"ohlr", 0xEC56, GR64, GR64, 0, 31, 32>;
+ def OLHR : FixedRotateSelectRIEf<"olhr", 0xEC56, GR64, GR64, 32, 63, 32>;
+ def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
+ def XHHR : FixedRotateSelectRIEf<"xhhr", 0xEC57, GR64, GR64, 0, 31>;
+ def XHLR : FixedRotateSelectRIEf<"xhlr", 0xEC57, GR64, GR64, 0, 31, 32>;
+ def XLHR : FixedRotateSelectRIEf<"xlhr", 0xEC57, GR64, GR64, 32, 63, 32>;
+ // 128 on I3 sets the T bit for the instruction
+ def RNSBGT : RotateSelectRIEf<"rnsbgt", 0xEC54, GR64, GR64, 128>;
+ def ROSBGT : RotateSelectRIEf<"rosbgt", 0xEC56, GR64, GR64, 128>;
+ def RXSBGT : RotateSelectRIEf<"rxsbgt", 0xEC57, GR64, GR64, 128>;
}
//===----------------------------------------------------------------------===//
@@ -2330,6 +2359,8 @@ defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>;
def JCT : MnemonicAlias<"jct", "brct">;
def JCTG : MnemonicAlias<"jctg", "brctg">;
+def JC : MnemonicAlias<"jc", "brc">;
+def JCTH : MnemonicAlias<"jcth", "brcth">;
def JAS : MnemonicAlias<"jas", "bras">;
def JASL : MnemonicAlias<"jasl", "brasl">;
def JXH : MnemonicAlias<"jxh", "brxh">;
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
index 9ce1a0d06b5af..3e87b2ed7ae9c 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
@@ -506,13 +506,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1553,5 +1554,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
index 120d4a457ee39..323262b831e3a 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
@@ -516,13 +516,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1643,5 +1644,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
+
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
index acba3a1fd9919..3a1eec594590e 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
@@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
//===----------------------------------------------------------------------===//
@@ -530,13 +531,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1689,5 +1691,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
index dd82b2b9b71e7..0a56fd78fb09b 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
@@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;
//===----------------------------------------------------------------------===//
@@ -530,13 +531,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat2, WLat2, FXa2, Cracked], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1722,5 +1724,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
index 226db9d4272f9..64bd642e0d2f8 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
@@ -469,13 +469,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1235,5 +1236,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===----------------------------------------------------------------------===//
+
+def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?$")>;
}
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
index f5ecdb1f43800..a8dfe3b0391c6 100644
--- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
+++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
@@ -480,13 +480,14 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;
// Rotate and insert
-def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
+def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;
// Rotate and Select
-def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "R(N|O|X)SBG(T)?$")>;
+def : InstRW<[WLat3, WLat3, FXU2, GroupAlone], (instregex "(N|O|X)(L|H)(L|H)R$")>;
//===----------------------------------------------------------------------===//
// Comparison
@@ -1280,5 +1281,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;
+//===----------------------------------------------------------------------===//
+// NOPs
+//===-------------------------------------...
[truncated]
|
redstar
reviewed
Jul 3, 2024
| @@ -973,6 +980,7 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { | |||
| def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; | |||
| def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; | |||
| } | |||
| def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>; | |||
There was a problem hiding this comment.
Suggested change
| def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>; | |
| def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>; |
Suggested change
| def LFI : InstAlias<"lfi\t$R1, $RI1",(IILF GR32:$R1, uimm32:$RI1)>; | |
| def LFI : InstAlias<"lfi\t$R1, $RI1", (IILF GR32:$R1, uimm32:$RI1)>; |
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| def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>; | ||
| def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>; |
There was a problem hiding this comment.
Suggested change
| def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>; | |
| def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>; | |
| def LLGFI : InstAlias<"llgfi\t$R1, $RI1", (LLILF GR64:$R1, imm64lf32:$RI1)>; | |
| def LLGHI : InstAlias<"llghi\t$R1, $RI1", (LLILL GR64:$R1, imm64ll16:$RI1)>; |
Suggested change
| def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>; | |
| def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>; | |
| def LLGFI : InstAlias<"llgfi\t$R1, $RI1",(LLILF GR64:$R1, imm64lf32:$RI1)>; | |
| def LLGHI : InstAlias<"llghi\t$R1, $RI1",(LLILL GR64:$R1, imm64ll16:$RI1)>; |
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| // def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; | ||
| // let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in | ||
| // def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; | ||
| // def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; | ||
| // def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; |
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No dead code in comments please.
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goddamnit. removed.
| @@ -363,7 +363,7 @@ class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> | |||
| let Inst{7-0} = op{7-0}; | |||
| } | |||
|
|
|||
| class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> | |||
| class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, bits<8> I3Or = 0, bits<8> I4Or = 0> | |||
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Not sure how serious this is applied to .td files, but the line is way over the 80 char limit. (Well, the original line is a little bit too long, too.)
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I split the line, similar to how it is done in the handful of other formats with extra parms.
|
The CI shows failures in insn-good.s and a bunch of SystemZ LLD tests, these definitely need to be addressed. Also, can you re-check that all mnemonics added here are also accepted by GAS? I think at least these may not be: nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr. You should verify that GAS can assemble all the insn-good* files (resulting in mostly identical object files - at least the disassembly of those object files needs to match again). |
These tests were expecting the old `bc 0, 0` / `bcr 0, %r0` disassemblies for nops. This commit changes them to expect the proper mnemonics in disassembly.
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I have fixed those tests. In
I moved the extended mnemonics of |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/11/builds/1712 Here is the relevant piece of the build log for the reference: |
|
follow-up build to the above is clean |
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This PR adds a number of thus-far missing extended mnemonics to the assembler and disassembler for SystemZ.
The following mnemonics have been added and are supported for the assembler and disassembler:
NOP(R)?LFIRISBG(N)?ZThe following mnemonics have been added and are supported for the assembler only:
JC(TH)?LLG(F|H)INOT(G)?R