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Merged
merged 7 commits into from
Jul 15, 2024
Merged

Add extended mnemonics #97571

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ba695e1
[SystemZ] Support Disassembly of NOP and NOPR
dominik-steenken Jul 3, 2024
5c3fe99
[SystemZ] Add missing instruction / mnemonic aliases
dominik-steenken Jul 3, 2024
8b5bc22
[SystemZ] Add NOTR and NOTGR for the AsmParser only
dominik-steenken Jul 3, 2024
673e6d7
[SystemZ] Introduce handling of T and Z bits for the RIE-f instructio…
dominik-steenken Jul 3, 2024
c7eb257
Clean up formatting and remove comments
dominik-steenken Jul 4, 2024
8f61af4
Fix insn-good.s test
dominik-steenken Jul 10, 2024
2601ac8
Fix linker tests
dominik-steenken Jul 10, 2024
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4 changes: 2 additions & 2 deletions lld/test/ELF/systemz-gotent-relax-und-dso.s
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Expand Up @@ -14,9 +14,9 @@
# DISASM: Disassembly of section .text:
# DISASM-EMPTY:
# DISASM-NEXT: <foo>:
# DISASM-NEXT: bc 0, 0
# DISASM-NEXT: nop 0
# DISASM: <hid>:
# DISASM-NEXT: bc 0, 0
# DISASM-NEXT: nop 0
# DISASM: <_start>:
# DISASM-NEXT: lgrl %r1, 0x2400
# DISASM-NEXT: lgrl %r1, 0x2400
Expand Down
4 changes: 2 additions & 2 deletions lld/test/ELF/systemz-gotent-relax.s
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Expand Up @@ -30,9 +30,9 @@

# DISASM: Disassembly of section .text:
# DISASM: 00000000010011e0 <foo>:
# DISASM-NEXT: bc 0, 0
# DISASM-NEXT: nop 0
# DISASM: 00000000010011e4 <hid>:
# DISASM-NEXT: bc 0, 0
# DISASM-NEXT: nop 0
# DISASM: 00000000010011e8 <ifunc>:
# DISASM-NEXT: br %r14
# DISASM: 00000000010011ea <_start>:
Expand Down
2 changes: 1 addition & 1 deletion lld/test/ELF/systemz-init-padding.s
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Expand Up @@ -12,7 +12,7 @@

# CHECK: <.init>:
# CHECK-NEXT: brasl %r14,
# CHECK-NEXT: bcr 0, %r7
# CHECK-NEXT: nopr %r7
# CHECK-NEXT: lg %r4, 272(%r15)

.text
Expand Down
6 changes: 3 additions & 3 deletions lld/test/ELF/systemz-plt.s
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Expand Up @@ -48,9 +48,9 @@
# DIS-NEXT: 100102c: d2 07 f0 30 10 08 mvc 48(8,%r15), 8(%r1)
# DIS-NEXT: 1001032: e3 10 10 10 00 04 lg %r1, 16(%r1)
# DIS-NEXT: 1001038: 07 f1 br %r1
# DIS-NEXT: 100103a: 07 00 bcr 0, %r0
# DIS-NEXT: 100103c: 07 00 bcr 0, %r0
# DIS-NEXT: 100103e: 07 00 bcr 0, %r0
# DIS-NEXT: 100103a: 07 00 nopr %r0
# DIS-NEXT: 100103c: 07 00 nopr %r0
# DIS-NEXT: 100103e: 07 00 nopr %r0
# DIS-NEXT: 1001040: c0 10 00 00 10 54 larl %r1, 0x10030e8
# DIS-NEXT: 1001046: e3 10 10 00 00 04 lg %r1, 0(%r1)
# DIS-NEXT: 100104c: 07 f1 br %r1
Expand Down
51 changes: 46 additions & 5 deletions llvm/lib/Target/SystemZ/SystemZInstrFormats.td
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Expand Up @@ -363,7 +363,8 @@ class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{7-0} = op{7-0};
}

class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstSystemZ<6, outs, ins, asmstr, pattern> {
field bits<48> Inst;
field bits<48> SoftFail = 0;
Expand All @@ -377,8 +378,22 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{47-40} = op{15-8};
let Inst{39-36} = R1;
let Inst{35-32} = R2;
let Inst{31-24} = I3;
let Inst{23-16} = I4;
let Inst{31} = !if(I3Or{7}, 1, I3{7});
let Inst{30} = !if(I3Or{6}, 1, I3{6});
let Inst{29} = !if(I3Or{5}, 1, I3{5});
let Inst{28} = !if(I3Or{4}, 1, I3{4});
let Inst{27} = !if(I3Or{3}, 1, I3{3});
let Inst{26} = !if(I3Or{2}, 1, I3{2});
let Inst{25} = !if(I3Or{1}, 1, I3{1});
let Inst{24} = !if(I3Or{0}, 1, I3{0});
let Inst{23} = !if(I4Or{7}, 1, I4{7});
let Inst{22} = !if(I4Or{6}, 1, I4{6});
let Inst{21} = !if(I4Or{5}, 1, I4{5});
let Inst{20} = !if(I4Or{4}, 1, I4{4});
let Inst{19} = !if(I4Or{3}, 1, I4{3});
let Inst{18} = !if(I4Or{2}, 1, I4{2});
let Inst{17} = !if(I4Or{1}, 1, I4{1});
let Inst{16} = !if(I4Or{0}, 1, I4{0});
let Inst{15-8} = I5;
let Inst{7-0} = op{7-0};
}
Expand Down Expand Up @@ -2349,6 +2364,12 @@ class AsmCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
mnemonic#"\t$R1, $R2", []>;

class NeverCondBranchRR<string mnemonic, bits<8> opcode>
: InstRR<opcode, (outs), (ins GR64:$R2),
mnemonic#"\t$R2", []> {
let R1 = 0;
}

class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
SDPatternOperator operator = null_frag>
: InstRR<opcode, (outs), (ins ADDR64:$R2),
Expand All @@ -2370,6 +2391,13 @@ class AsmCondBranchRX<string mnemonic, bits<8> opcode>
(ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$M1, $XBD2", []>;

class NeverCondBranchRX<string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs),
(ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
mnemonic#"\t$XBD2", []> {
let M1 = 0;
}

class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
: InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
!subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
Expand Down Expand Up @@ -3439,6 +3467,19 @@ class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
let OpType = "reg";
}


class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
RegisterOperand cls1, RegisterOperand cls2>
: InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3),
mnemonic#"\t$R1, $R2",
[(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> {
let R3 = R2;
let M4 = 0;
let OpKey = mnemonic#cls1;
let OpType = "reg";
}


multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
SDPatternOperator operator, RegisterOperand cls1,
RegisterOperand cls2> {
Expand Down Expand Up @@ -4999,11 +5040,11 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
}

class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2>
RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0>
: InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
imm32zx8:$I5),
mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";
}
Expand Down
23 changes: 18 additions & 5 deletions llvm/lib/Target/SystemZ/SystemZInstrInfo.td
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Expand Up @@ -111,11 +111,11 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
// NOPs. These are again variants of the conditional branches, with the
// condition mask set to "never". NOP_bare can't be an InstAlias since it
// would need R0D hard coded which is not part of ADDR64BitRegClass.
def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>;
def NOP : NeverCondBranchRX<"nop", 0x47>;
let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in
def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>;
def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>;
def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>;
def NOPR : NeverCondBranchRR<"nopr", 0x07>;
def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>;

// An alias of BRC 0, label
def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>;
Expand Down Expand Up @@ -464,6 +464,8 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
}
def LLGFI : InstAlias<"llgfi\t$R1, $RI1", (LLILF GR64:$R1, imm64lf32:$RI1)>;
def LLGHI : InstAlias<"llghi\t$R1, $RI1", (LLILL GR64:$R1, imm64ll16:$RI1)>;

// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in {
Expand Down Expand Up @@ -973,6 +975,7 @@ let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
}
def LFI : InstAlias<"lfi\t$R1, $RI1", (IILF GR32:$R1, uimm32:$RI1)>;
def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;

Expand Down Expand Up @@ -1372,6 +1375,10 @@ let Predicates = [FeatureMiscellaneousExtensions3],
let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>;
def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>;
let isAsmParserOnly = 1 in {
def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>;
def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>;
}
}

// NXOR.
Expand Down Expand Up @@ -1526,13 +1533,17 @@ def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>;
let Defs = [CC] in {
let isCodeGenOnly = 1 in
def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
let CCValues = 0xE, CompareZeroCCMask = 0xE in
let CCValues = 0xE, CompareZeroCCMask = 0xE in {
def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>;
}
}

// On zEC12 we have a variant of RISBG that does not set CC.
let Predicates = [FeatureMiscellaneousExtensions] in
let Predicates = [FeatureMiscellaneousExtensions] in {
def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>;
}

// Forms of RISBG that only affect one word of the destination register.
// They do not set CC.
Expand Down Expand Up @@ -2330,6 +2341,8 @@ defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>;

def JCT : MnemonicAlias<"jct", "brct">;
def JCTG : MnemonicAlias<"jctg", "brctg">;
def JC : MnemonicAlias<"jc", "brc">;
def JCTH : MnemonicAlias<"jcth", "brcth">;
def JAS : MnemonicAlias<"jas", "bras">;
def JASL : MnemonicAlias<"jasl", "brasl">;
def JXH : MnemonicAlias<"jxh", "brxh">;
Expand Down
8 changes: 7 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
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Expand Up @@ -506,9 +506,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;

// Rotate and insert
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;

// Rotate and Select
Expand Down Expand Up @@ -1553,5 +1553,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;

//===----------------------------------------------------------------------===//
// NOPs
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;

}

8 changes: 7 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
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Expand Up @@ -516,9 +516,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;

// Rotate and insert
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;

// Rotate and Select
Expand Down Expand Up @@ -1643,5 +1643,11 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;

//===----------------------------------------------------------------------===//
// NOPs
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;

}

8 changes: 7 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
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Expand Up @@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -530,9 +531,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;

// Rotate and insert
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;

// Rotate and Select
Expand Down Expand Up @@ -1689,5 +1690,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;

//===----------------------------------------------------------------------===//
// NOPs
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}

8 changes: 7 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
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Expand Up @@ -471,6 +471,7 @@ def : InstRW<[WLat1, FXa, NormalGr], (instregex "NC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "OC(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NN(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NO(G)?RK$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NOT(G)?R$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "NX(G)?RK$")>;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -530,9 +531,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXa4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXa, LSU, NormalGr], (instregex "RLL(G)?$")>;

// Rotate and insert
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXa, NormalGr], (instregex "RISBMux$")>;

// Rotate and Select
Expand Down Expand Up @@ -1722,5 +1723,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPE?I$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;

//===----------------------------------------------------------------------===//
// NOPs
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, FXb, NormalGr], (instregex "NOP(R)?$")>;
}

7 changes: 6 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
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Expand Up @@ -469,9 +469,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;

// Rotate and insert
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;

// Rotate and Select
Expand Down Expand Up @@ -1235,5 +1235,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;

//===----------------------------------------------------------------------===//
// NOPs
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, LSU, EndGroup], (instregex "NOP(R)?$")>;
}

7 changes: 6 additions & 1 deletion llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
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Expand Up @@ -480,9 +480,9 @@ def : InstRW<[WLat5LSU, WLat5LSU, FXU4, LSU, GroupAlone2],
def : InstRW<[WLat2LSU, FXU, LSU, NormalGr], (instregex "RLL(G)?$")>;

// Rotate and insert
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBH(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBL(G|H|L)$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBG(N|32)?(Z)?$")>;
def : InstRW<[WLat1, FXU, NormalGr], (instregex "RISBMux$")>;

// Rotate and Select
Expand Down Expand Up @@ -1280,5 +1280,10 @@ def : InstRW<[WLat30, MCD], (instregex "STC(PS|RW)$")>;
def : InstRW<[WLat30, MCD], (instregex "TPI$")>;
def : InstRW<[WLat30, MCD], (instregex "SAL$")>;

//===----------------------------------------------------------------------===//
// NOPs
//===----------------------------------------------------------------------===//

def : InstRW<[WLat1, LSU, NormalGr], (instregex "NOP(R)?$")>;
}

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