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[CodeGen] Remove checks for vectors in unsigned division prior to computing leading zeros #99524

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merged 2 commits into from
Jul 19, 2024

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AZero13
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@AZero13 AZero13 commented Jul 18, 2024

It turns out we can safely use DAG.computeKnownBits(N0).countMinLeadingZeros() with constant legal vectors, so remove the check for it.

@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Jul 18, 2024
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llvmbot commented Jul 18, 2024

@llvm/pr-subscribers-backend-x86
@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-llvm-selectiondag

Author: AtariDreams (AtariDreams)

Changes

It turns out that the function already exits early if N1 is not a constant or is a vector, so simplify.


Full diff: https://github.com/llvm/llvm-project/pull/99524.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (+10-10)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index c3a20b5044c5f..7e38a3607cdd1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -6483,15 +6483,7 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
 
   // Try to use leading zeros of the dividend to reduce the multiplier and
   // avoid expensive fixups.
-  // TODO: Support vectors.
-  unsigned LeadingZeros = 0;
-  if (!VT.isVector() && isa<ConstantSDNode>(N1)) {
-    assert(!isOneConstant(N1) && "Unexpected divisor");
-    LeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
-    // UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros in
-    // the dividend exceeds the leading zeros for the divisor.
-    LeadingZeros = std::min(LeadingZeros, N1->getAsAPIntVal().countl_zero());
-  }
+  unsigned KnownLeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
 
   bool UseNPQ = false, UsePreShift = false, UsePostShift = false;
   SmallVector<SDValue, 16> PreShifts, PostShifts, MagicFactors, NPQFactors;
@@ -6509,8 +6501,16 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
       PreShift = PostShift = DAG.getUNDEF(ShSVT);
       MagicFactor = NPQFactor = DAG.getUNDEF(SVT);
     } else {
+
+      // Try to use leading zeros of the dividend to reduce the multiplier and
+      // avoid expensive fixups.
+      unsigned LeadingZeros = DAG.computeKnownBits(N0).countMinLeadingZeros();
+      // UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros
+      // in the dividend exceeds the leading zeros for the divisor.
+      LeadingZeros = std::min(LeadingZeros, N1->getAsAPIntVal().countl_zero());
       UnsignedDivisionByConstantInfo magics =
-          UnsignedDivisionByConstantInfo::get(Divisor, LeadingZeros);
+          UnsignedDivisionByConstantInfo::get(
+              Divisor, std::min(KnownLeadingZeros, Divisor.countl_zero()));
 
       MagicFactor = DAG.getConstant(magics.Magic, dl, SVT);
 

@dtcxzyw dtcxzyw requested a review from RKSimon July 18, 2024 16:33
@AZero13 AZero13 force-pushed the vectordiv branch 2 times, most recently from 8212034 to a88be64 Compare July 18, 2024 18:21
@AZero13 AZero13 force-pushed the vectordiv branch 2 times, most recently from 0086f0a to 14cd7d6 Compare July 18, 2024 18:27
@AZero13 AZero13 changed the title [SelectionDAG] Remove redundant vector checks (NFC) [CodeGen] Remove redundant vector checks (NFC) Jul 18, 2024
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topperc commented Jul 18, 2024

There's only an early exit for vector in the TargetLowering code if the type isn't legal.

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I don't think this patch is NFC

@AZero13 AZero13 changed the title [CodeGen] Remove redundant vector checks (NFC) [CodeGen] Remove redundant vector checks Jul 18, 2024
@AZero13 AZero13 force-pushed the vectordiv branch 2 times, most recently from 1dc4327 to 0f54cfc Compare July 18, 2024 18:48
@AZero13 AZero13 requested a review from topperc July 18, 2024 18:48
@AZero13 AZero13 changed the title [CodeGen] Remove redundant vector checks [CodeGen] Remove redundant checks Jul 18, 2024
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topperc commented Jul 18, 2024

This patch changes the generated code for this test for x86-64

define <4 x i32> @foo(<4 x i32> %x) {                                            
  %a = and <4 x i32> %x, <i32 255, i32 255, i32 255, i32 255>                    
  %b = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>                           
  ret <4 x i32> %b                                                               
} 

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topperc commented Jul 18, 2024

It turns out we can safely use DAG.computeKnownBits(N0).countMinLeadingZeros() with constant legal vectors, so remove the check for it.

It is safe, but you have to write tests for it.

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AZero13 commented Jul 18, 2024

define <4 x i32> @foo(<4 x i32> %x) {

I actually added this check to avoid unforeseen bugs and turns out that was bad on my part. But yeah I will add the test now.

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topperc commented Jul 18, 2024

define <4 x i32> @foo(<4 x i32> %x) {

I actually added this check to avoid unforeseen bugs and turns out that was bad on my part. But yeah I will add the test now.

What check did you add? The original code in TargetLowering was written by me. https://reviews.llvm.org/D140750 I specifically didn't do vectors at the time because I hadn't thought through the math. As I wrote at the time:

"Wasn't sure if we need to apply the clip by divisor leading zeros uniformly across the whole vector when there are different divisors which would require another loop over the divisors. Or if we could treat each element individually and apply a clip inside BuildUDIVPattern."

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Add back request changes until tests are added.

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AZero13 commented Jul 18, 2024

Add back request changes until tests are added.

define <4 x i32> @foo(<4 x i32> %x) {

I actually added this check to avoid unforeseen bugs and turns out that was bad on my part. But yeah I will add the test now.

What check did you add? The original code in TargetLowering was written by me. https://reviews.llvm.org/D140750 I specifically didn't do vectors at the time because I hadn't thought through the math. As I wrote at the time:

"Wasn't sure if we need to apply the clip by divisor leading zeros uniformly across the whole vector when there are different divisors which would require another loop over the divisors. Or if we could treat each element individually and apply a clip inside BuildUDIVPattern."

My bad, I was confusing selectiondag and globalisel

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topperc commented Jul 18, 2024

PR title needs to be updated. As we've now shown, they were never redundant.

@AZero13 AZero13 changed the title [CodeGen] Remove redundant checks [CodeGen] Remove checks for vectors Jul 18, 2024
@AZero13 AZero13 changed the title [CodeGen] Remove checks for vectors [CodeGen] Remove checks for vectors in unsigned division prior to computing leading zeros Jul 18, 2024
@AZero13 AZero13 requested a review from topperc July 18, 2024 19:30
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AZero13 commented Jul 18, 2024

PR title needs to be updated. As we've now shown, they were never redundant.

Fixed!

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LGTM

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AZero13 commented Jul 18, 2024

@topperc This should be good to go now! Thank you!

Please note I do not have commit perms...

AZero13 added 2 commits July 18, 2024 17:56
…puting leading zeros

It turns out we can safely use DAG.computeKnownBits(N0).countMinLeadingZeros() with constant legal vectors, so remove the check for it.
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LGTM

@KanRobert KanRobert merged commit 8717407 into llvm:main Jul 19, 2024
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@AZero13 AZero13 deleted the vectordiv branch July 19, 2024 04:17
yuxuanchen1997 pushed a commit that referenced this pull request Jul 25, 2024
…puting leading zeros (#99524)

Summary:
It turns out we can safely use
DAG.computeKnownBits(N0).countMinLeadingZeros() with constant legal
vectors, so remove the check for it.

Test Plan: 

Reviewers: 

Subscribers: 

Tasks: 

Tags: 


Differential Revision: https://phabricator.intern.facebook.com/D60251562
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5 participants