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add a Cargo feature, cm7-r0p1, to fix a Cortex-M7 BASEPRI erratum #72

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Jan 11, 2018
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5 changes: 4 additions & 1 deletion .travis.yml
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,10 @@ script:

after_script: set +e

cache: cargo
cache:
cargo: true
directories:
- $HOME/.xargo

before_cache:
- chmod -R a+r $HOME/.cargo;
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5 changes: 4 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -12,4 +12,7 @@ version = "0.3.1"
[dependencies]
aligned = "0.1.1"
bare-metal = "0.1.0"
volatile-register = "0.2.0"
volatile-register = "0.2.0"

[features]
cm7-r0p1 = []
4 changes: 4 additions & 0 deletions ci/script.sh
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,10 @@ set -euxo pipefail

main() {
case $TARGET in
thumbv7em-none-eabi*)
xargo check --target $TARGET --features cm7-r0p1
xargo check --target $TARGET
;;
thumbv*-none-eabi*)
xargo check --target $TARGET
;;
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15 changes: 13 additions & 2 deletions src/register/basepri.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,22 @@ pub fn read() -> u8 {
}

/// Writes to the CPU register
///
/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
#[inline]
pub unsafe fn write(_basepri: u8) {
pub unsafe fn write(basepri: u8) {
match () {
#[cfg(target_arch = "arm")]
() => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
() => match () {
#[cfg(not(feature = "cm7-r0p1"))]
() => asm!("msr BASEPRI, $0" :: "r"(basepri) : "memory" : "volatile"),
#[cfg(feature = "cm7-r0p1")]
() => asm!("cpsid i
msr BASEPRI, $0
cpsie i" :: "r"(basepri) : "memory" : "volatile"),
},
#[cfg(not(target_arch = "arm"))]
() => unimplemented!(),
}
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15 changes: 13 additions & 2 deletions src/register/basepri_max.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,23 @@
///
/// - `basepri != 0` AND `basepri::read() == 0`, OR
/// - `basepri != 0` AND `basepri < basepri::read()`
///
/// **IMPORTANT** If you are using a Cortex-M7 device with revision r0p1 you MUST enable the
/// `cm7-r0p1` Cargo feature or this function WILL misbehave.
#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
#[inline]
pub fn write(_basepri: u8) {
pub fn write(basepri: u8) {
match () {
#[cfg(target_arch = "arm")]
() => unsafe {
asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile");
match () {
#[cfg(not(feature = "cm7-r0p1"))]
() => asm!("msr BASEPRI_MAX, $0" :: "r"(basepri) : "memory" : "volatile"),
#[cfg(feature = "cm7-r0p1")]
() => asm!("cpsid i
msr BASEPRI_MAX, $0
cpsie i" :: "r"(basepri) : "memory" : "volatile"),
}
},
#[cfg(not(target_arch = "arm"))]
() => unimplemented!(),
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