Cp/r145014653 add support for riscv32 macho corefiles #10540
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Add the enum values for MachO RISC-V CPU type and CPU subtype to llvm and use in LLDB's ArchSpec. (cherry picked from commit 213424b)
Add support for reading a macho corefile with CPU_TYPE_RISCV and the riscv32 general purpose register file. I added code for the floating point and exception registers too, but haven't exercised this. If we start putting the full CSR register bank in a riscv corefile, it'll be in separate 4k byte chunks, but I don't have a corefile to test against that so I haven't written the code to read it. The RegisterContextDarwin_riscv32 is copied & in the style of the other RegisterContextDarwin classes; it's not the first choice I would make for representing this, but it wasn't worth changing for this cputype. rdar://145014653 (cherry picked from commit 096ab51)
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JDevlieghere
approved these changes
Apr 24, 2025
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