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Bring FPGA-Test-Shield tests into Mbed-os master. #10820

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Merged
merged 6 commits into from
Jul 4, 2019

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mprse
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@mprse mprse commented Jun 13, 2019

Description

Bring FPGA-Test-Shield tests to Mbed-os.

When this is merged these tests can be removed from ci-tes-shield-fpga repository.

By default, all these tests will be skipped on CI. To enable these tests FPGA_CI_TEST_SHIELD component must be added in targets.json configuration file.

Related PRs: PR #10816

Pull request type

[ ] Fix
[ ] Refactor
[ ] Target update
[ ] Functionality change
[ ] Docs update
[X] Test update
[ ] Breaking change

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@maciejbocianski
@fkjagodzinski
@c1728p9
@jamesbeyond

@ciarmcom
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@mprse, thank you for your changes.
@fkjagodzinski @maciejbocianski @jamesbeyond @c1728p9 @ARMmbed/mbed-os-hal @ARMmbed/mbed-os-test @ARMmbed/mbed-os-maintainers please review.

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@maciejbocianski @jamesbeyond could you review please ?

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These tests are HAL tests, shall we add the header files for the test along with doxygen comments. (same as rest of the hal tests)
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c1728p9 commented Jun 28, 2019

@jamesbeyond it would be good to have header files with doxygen comments for the APIs which have a HAL specification. This should map the defined behavior to tests which validates it.

#error [NOT_SUPPORTED] I2C not supported for this target
#elif !COMPONENT_FPGA_CI_TEST_SHIELD
#error [NOT_SUPPORTED] FPGA CI Test Shield is needed to run this test
#elif !defined(FULL_TEST_SHIELD)
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FULL_TEST_SHIELD should probably be removed since this only applies to the Basys3.

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Fixed

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mprse commented Jun 29, 2019

These tests are HAL tests, shall we add the header files for the test along with doxygen comments. (same as rest of the hal tests)

We missed that while working on FPGA tests. I agree that headers should be added. I will add when I come back to the office.

Divide one test case to four test cases to increase readability.
Adapted to the last version of the FPGA CI Test Shield API.
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mprse commented Jul 3, 2019

Pushed last changes provided by @maciejbocianski to FPGA I2C test (261e67b).

Removed FULL_TEST_SHIELD from FPGA analogin test(5ffa260).

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mprse commented Jul 3, 2019

At the moment we do not have HAL specification for the tested APIs here. We can add headers when HAL specification is ready and we need headers to map the test cases to the defined behavior.

I think we should move forward with this PR. It is hard now to keep consistency between FPGA repo and this one. Even if some dummy headers are required we can add this in the additional PR.

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Before I approve, just one comment about dead code below.

Where is the documentation for fpga testing (reference for docs PR?), plus what these are testing - I am seeing just test files here and defined test cases but where is the test plan (or something similar) or is all suficient what we have in Cases() in the files?

// printf("Sum: %llu\r\n", sum);
// printf("Num power samples: %d\r\n", samples);
// printf("Num power cycles: %llu\r\n", cycles);
// printf("ANIN0 voltage: %.6fV\r\n", tester.get_anin_voltage(0));
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Can we remove these lines not used?

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I think that this code has been added for debugging. Maybe I can wrap this code around #if DEBUG directive?

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Fixed

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0xc0170 commented Jul 3, 2019

Is this OK to go to 5.13.2 (in 2 weeks time) , landing to master once it's ready?

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mprse commented Jul 3, 2019

Before I approve, just one comment about dead code below.

Where is the documentation for fpga testing (reference for docs PR?), plus what these are testing - I am seeing just test files here and defined test cases but where is the test plan (or something similar) or is all suficient what we have in Cases() in the files?

It looks like we do not have HAL specification ready for the tested APIs. I would consider these tests as general tests to show the capabilities of the FPGA Test Shields for the SiP workshop.
The plan is to add dummy test headers with given/when/then description in the separate PR.

Header file and mapping between test cases and defined behavior will be added to this PR:
#10816

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mprse commented Jul 3, 2019

Is this OK to go to 5.13.2 (in 2 weeks time) , landing to master once it's ready?

cc @jamesbeyond
I think we need this for the next week...

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Hi @0xc0170, this PR is for workshop next week, please mark this as high importance.

… tolerance

Keep "AnalogIn - full test" disabled due to hardware issue in the first rev of FPGA Test Shield.
@mprse mprse force-pushed the bring_fpga_tests_master branch from 5ffa260 to c6acc85 Compare July 3, 2019 10:33
@mprse mprse force-pushed the bring_fpga_tests_master branch from c6acc85 to c016f2a Compare July 3, 2019 10:34
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mprse commented Jul 3, 2019

@0xc0170 Ready for CI.

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After a offline conversation, I'd agree that because we don't have defined behavior for current these HAL APIs, the test header files can come to the repo as separate PR

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mprse commented Jul 4, 2019

This one does not need preceding PR. It is ready for CI.

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0xc0170 commented Jul 4, 2019

This one does not need preceding PR. It is ready for CI.

I am reviewing at the moment

Case("115200, 8N1, FC on", one_peripheral<UARTPort, DefaultFormFactor, test_common<115200, 8, ParityNone, 1> >),
Case("115200, 8N1, FC off", one_peripheral<UARTNoFCPort, DefaultFormFactor, test_common_no_fc<115200, 8, ParityNone, 1> >), // DISCO_L475VG_IOT01A
// data bits
/* FIXME not supported: K64F
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do we need to keep this dead code here? Can it be tracked separately (removed from here, stashed somewhere else with the tracking issue for this)

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@fkjagodzinski Can you check this?

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Ok, so I checked this part -- data bits on K64F.

  1. Our HAL allows setting data_bits and does not restrict this value in any way:

    mbed-os/hal/serial_api.h

    Lines 137 to 144 in b55344c

    /** Configure the format. Set the number of bits, parity and the number of stop bits
    *
    * @param obj The serial object
    * @param data_bits The number of data bits
    * @param parity The parity
    * @param stop_bits The number of stop bits
    */
    void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
  2. The HAL implementation for K64F does not really use data_bits param:
    void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
  3. ... and this is because the fsl_uart.c does not have any data_bits-related config item:
    /*! @brief UART configuration structure. */
    typedef struct _uart_config
    {
    uint32_t baudRate_Bps; /*!< UART baud rate */
    uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
    #if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
    uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
    #endif
    #if defined(FSL_FEATURE_UART_HAS_FIFO) && FSL_FEATURE_UART_HAS_FIFO
    uint8_t txFifoWatermark; /*!< TX FIFO watermark */
    uint8_t rxFifoWatermark; /*!< RX FIFO watermark */
    #endif
    bool enableTx; /*!< Enable TX */
    bool enableRx; /*!< Enable RX */
    } uart_config_t;
  4. However, the K64 Sub-Family Reference Manual says there are two settings:
Programmable 8-bit or 9-bit data format

Initially I thought we should uncomment this block of code and expect NXP to provide a fix. Now, knowing NXP would have to update their HAL, I don't think it would be reasonable to do so. Also, I'm not so sure if Mbed OS should require support of 9-bit UART data at all.

@jamesbeyond, what do you think about this? Should I remove the data_bits part of this test?
BTW, there are two more similar FIXME comments regarding ST targets. Remove these as well? (don't know why they fail yet).

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I vote for yes. dead code should be removed (tracking issue to have this, with commit including the changes needed). It will be easy to bring this back once it is fixed

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Fixed (d2d3d5f)

Case("AnalogIn - init test", all_ports<AnaloginPort, DefaultFormFactor, analogin_init>),
// This test case is disabled for now due to hardware issue in the first rev of FPGA Test Shield
#if 0
Case("AnalogIn - full test", all_ports<AnaloginPort, DefaultFormFactor, analogin_full_test>),
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remove as well this one not used

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This one will be enabled as soon as we get the rev.2 of the FPGA-Test-Shield and I will be able to rework and execute this test case.

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It should come with rv2 (we should not have if 0 in the code)

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Ok, I will remove this test case for now and add it later.

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fixed (879d891)

#include "test_utils.h"


#define pwm_debug_printf(...)
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Empty?

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This is macro for debugging. By default, it does nothing.

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OK, I was expecting if debug , it does something

The test case which checks full range cannot be executed at the moment due to a hardware bug in FPGA-Test-Shield.
This test case will be restored when the final version of FPGA-Test-Shield is ready.
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0xc0170 commented Jul 4, 2019

CI started meanwhile

Not all uart features are supported by specific platforms.
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0xc0170 commented Jul 4, 2019

Restarted CI after latest changes

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mbed-ci commented Jul 4, 2019

Test run: FAILED

Summary: 1 of 4 test jobs failed
Build number : 1
Build artifacts

Failed test jobs:

  • jenkins-ci/mbed-os-ci_greentea-test

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mbed-ci commented Jul 4, 2019

Test run: SUCCESS

Summary: 4 of 4 test jobs passed
Build number : 2
Build artifacts

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9 participants