[SYCL] Support USM buffer location property in malloc_host #6220
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8b86af77b872c58b0c68e53b0495350c5bc4dd9c passes HIP but still fails L0: |
sycl/source/detail/usm/usm_impl.cpp
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| const platform &Platform = Ctxt.get_platform(); | ||
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| std::vector<pi_usm_mem_properties> Props; | ||
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| if (Platform.has_extension("cl_intel_mem_alloc_buffer_location") && | ||
| PropList.has_property<cl::sycl::ext::intel::experimental::property:: | ||
| usm::buffer_location>()) { | ||
| Props.emplace_back(PI_MEM_USM_ALLOC_BUFFER_LOCATION); | ||
| Props.emplace_back( | ||
| PropList | ||
| .get_property<cl::sycl::ext::intel::experimental::property:: | ||
| usm::buffer_location>() | ||
| .get_buffer_location()); | ||
| } | ||
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| if (Props.empty()) { | ||
| // Explicitly pass null pointer since the OpenCL driver may not support | ||
| // empty property lists, i.e., containing only a null terminator. | ||
| Error = Plugin.call_nocheck<PiApiKind::piextUSMHostAlloc>( | ||
| &RetVal, C, nullptr, Size, Alignment); | ||
| } else { | ||
| Props.emplace_back(0); // null-terminate property list | ||
| Error = Plugin.call_nocheck<PiApiKind::piextUSMHostAlloc>( | ||
| &RetVal, C, Props.data(), Size, Alignment); | ||
| } | ||
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this property has no effect when passed to sycl::malloc_shared() or sycl::malloc_host()
so why is this code not ignoring it?
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The spec is being updated to not say that: #6219
@smaslov-intel Could you help us resolve this failure? |
@tiwaria1 : please show the test output before and after the change |
Hi @smaslov-intel, how do I get this build, do I have to build this change locally or is there a way to download the build from github for this PR? And do you know where the llvm_test_suite is located on the repo? The failing test is usm_pooling.cpp. |
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@tiwaria1 I believe this is the failing test: llvm-test-suite/SYCL/USM/usm_pooling.cpp. |
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See #6218 (comment) for unrelated ESIMD Emu runner breakage. |
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After trying many slight variations of this PR, I am unsure why L0 GEN9 is failing in |
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@smaslov-intel, @cperkinsintel Do you have access to L0 GEN9 platform, could you help us get access to debug this further? Should I file an issue on intel/llvm-test-suite to see if the test owner can help us understand the test? |
@tiwaria1 : yes, that's what it is testing, expects specific calls to native L0 RT based on the SYCL USM pooling settings. With your changes do you expect any difference in PI calls being made by SYCL RT for the failing test? (I don't think so, and then the failure does look unexpected).
Absolutely. @pvchupin : do we have any wiki on how to locally reproduce L0 failures encountered in CI testing? |
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9f7c265 is failing check-clang with an unrelated error, see #6243 (comment): |
This seems to be introduced by 4071659 a few hours ago. |
You need to follow https://github.com/intel/llvm/blob/sycl/sycl/doc/GetStartedGuide.md and may also need to pass --ci-defaults to the configure.py to match extended testing CI is doing. |
Thanks @smaslov-intel! I have rebased onto |
Please see https://github.com/intel/llvm/pull/6220/files#r891017817 |
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The change looks good, and what about #6220 (comment)? |
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@smaslov-intel, this PR is ready for review. Thank you for investigating and providing the pointers that helped quickly resolve the test failure 🙂 |
smaslov-intel
approved these changes
Jun 8, 2022
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@intel/llvm-gatekeepers This is ready for merge 🙂 |
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See malloc_shared implementation in #6218
See extension specification in #6219
@tiwaria1 @bsyrowik @GarveyJoe @aditikum @ajaykumarkannan