[PowerPC] Add custom lowering for ssubo (#111748) #115875
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@llvm/pr-subscribers-backend-powerpc Author: Maryam Moghadas (maryammo) ChangesThis patch is to improve the codegen for ssubo node for i32 in 64-bit mode by custom lowering. Full diff: https://github.com/llvm/llvm-project/pull/115875.diff 3 Files Affected:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index ec4f8f4be425ed..51c86cd937378e 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -200,6 +200,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom);
+ // On P10, the default lowering generates better code using the
+ // setbc instruction.
+ if (!Subtarget.hasP10Vector() && isPPC64)
+ setOperationAction(ISD::SSUBO, MVT::i32, Custom);
+
// Match BITREVERSE to customized fast code sequence in the td file.
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
@@ -12020,6 +12025,27 @@ SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
return Res;
}
+SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {
+
+ SDLoc dl(Op);
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
+
+ SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, LHS, RHS);
+
+ SDValue Xor1 = DAG.getNode(ISD::XOR, dl, MVT::i32, RHS, LHS);
+ SDValue Xor2 = DAG.getNode(ISD::XOR, dl, MVT::i32, Sub, LHS);
+
+ SDValue And = DAG.getNode(ISD::AND, dl, MVT::i32, Xor1, Xor2);
+
+ SDValue Overflow = DAG.getNode(ISD::SRL, dl, MVT::i32, And,
+ DAG.getConstant(31, dl, MVT::i32));
+ SDValue OverflowTrunc =
+ DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow);
+
+ return DAG.getMergeValues({Sub, OverflowTrunc}, dl);
+}
+
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
@@ -12042,6 +12068,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::SETCC: return LowerSETCC(Op, DAG);
case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
+ case ISD::SSUBO:
+ return LowerSSUBO(Op, DAG);
case ISD::INLINEASM:
case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG);
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 0adbad86845973..dde45e4cf6f4ae 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1279,6 +1279,7 @@ namespace llvm {
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
index fd5f26ba35742f..4c11f7f919a3ca 100644
--- a/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
+++ b/llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
@@ -129,12 +129,11 @@ entry:
define i1 @test_ssubo_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_ssubo_i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sub 5, 3, 4
-; CHECK-NEXT: cmpwi 1, 4, 0
-; CHECK-NEXT: cmpw 5, 3
-; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: creqv 20, 5, 0
-; CHECK-NEXT: isel 3, 0, 3, 20
+; CHECK-NEXT: xor 5, 4, 3
+; CHECK-NEXT: sub 4, 3, 4
+; CHECK-NEXT: xor 3, 4, 3
+; CHECK-NEXT: and 3, 5, 3
+; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr
entry:
%res = call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %a, i32 %b) nounwind
|
maryammo
requested review from
stefanp-synopsys,
RolandF77,
syzaara and
amy-kwan
RolandF77
reviewed
Nov 26, 2024
| @@ -200,6 +200,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, | |||
|
|
|||
| setOperationAction(ISD::UADDO, isPPC64 ? MVT::i64 : MVT::i32, Custom); | |||
|
|
|||
| // On P10, the default lowering generates better code using the | |||
| // setbc instruction. | |||
| if (!Subtarget.hasP10Vector() && isPPC64) | |||
There was a problem hiding this comment.
I pre committed a test and will enable this for 32-bit.
The reason to pre-commit a test was to have run lines for aix64/aix32. Adding those to the existing test would make a lot of changes unrelated to this patch. Thanks.
This patch is to improve the codegen for ssubo node for i32 in 64-bit mode by custom lowering.
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/171/builds/11282 Here is the relevant piece of the build log for the reference |
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/73/builds/9319 Here is the relevant piece of the build log for the reference |
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This patch is to improve the codegen for ssubo node for i32 in 64-bit mode by custom lowering.