[CodeGen][NPM] Port VirtRegRewriter to NPM #130564
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@llvm/pr-subscribers-llvm-regalloc Author: Akshat Oke (optimisan) ChangesNot sure why this is squished into VirtRegMap.h Full diff: https://github.com/llvm/llvm-project/pull/130564.diff 12 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index c9e405e1981d9..f5fba0d65401e 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -235,6 +235,21 @@ class VirtRegMapPrinterPass : public PassInfoMixin<VirtRegMapPrinterPass> {
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
+
+class VirtRegRewriterPass : public PassInfoMixin<VirtRegRewriterPass> {
+ bool ClearVirtRegs = true;
+
+public:
+ VirtRegRewriterPass(bool ClearVirtRegs = true)
+ : ClearVirtRegs(ClearVirtRegs) {}
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ static bool isRequired() { return true; }
+
+ void printPipeline(raw_ostream &OS, function_ref<StringRef(StringRef)>) const;
+};
+
} // end llvm namespace
#endif // LLVM_CODEGEN_VIRTREGMAP_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 9afca6c0dab70..b8b0d09b917fb 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -316,7 +316,7 @@ void initializeUnreachableBlockElimLegacyPassPass(PassRegistry &);
void initializeUnreachableMachineBlockElimPass(PassRegistry &);
void initializeVerifierLegacyPassPass(PassRegistry &);
void initializeVirtRegMapWrapperLegacyPass(PassRegistry &);
-void initializeVirtRegRewriterPass(PassRegistry &);
+void initializeVirtRegRewriterLegacyPass(PassRegistry &);
void initializeWasmEHPreparePass(PassRegistry &);
void initializeWinEHPreparePass(PassRegistry &);
void initializeWriteBitcodePassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 9ec9836c15eb5..db227ddaa0e2b 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -81,6 +81,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TwoAddressInstructionPass.h"
#include "llvm/CodeGen/UnreachableBlockElim.h"
+#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/CodeGen/WasmEHPrepare.h"
#include "llvm/CodeGen/WinEHPrepare.h"
#include "llvm/IR/PassManager.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 87253ebc8b789..eab6a6f6cd494 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -215,6 +215,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "virt-reg-rewriter", "VirtRegRewriterPass",
+ [](bool ClearVirtRegs) { return VirtRegRewriterPass(ClearVirtRegs); },
+ parseVirtRegRewriterPassOptions, "no-clear-vregs;clear-vregs")
+
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved from
@@ -287,6 +293,5 @@ DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass)
DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass)
DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass)
DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass)
-DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass)
DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass)
#undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 3169a109aa174..b3ec59889b8b7 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -141,7 +141,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeUnreachableBlockElimLegacyPassPass(Registry);
initializeUnreachableMachineBlockElimPass(Registry);
initializeVirtRegMapWrapperLegacyPass(Registry);
- initializeVirtRegRewriterPass(Registry);
+ initializeVirtRegRewriterLegacyPass(Registry);
initializeWasmEHPreparePass(Registry);
initializeWinEHPreparePass(Registry);
initializeXRayInstrumentationPass(Registry);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0fc3e5d9a3052..a00f6bc0bf3ae 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -197,7 +197,7 @@ VirtRegMap VirtRegMapAnalysis::run(MachineFunction &MF,
//
namespace {
-class VirtRegRewriter : public MachineFunctionPass {
+class VirtRegRewriter {
MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
const TargetInstrInfo *TII = nullptr;
@@ -223,9 +223,21 @@ class VirtRegRewriter : public MachineFunctionPass {
public:
static char ID;
- VirtRegRewriter(bool ClearVirtRegs_ = true) :
- MachineFunctionPass(ID),
- ClearVirtRegs(ClearVirtRegs_) {}
+ VirtRegRewriter(bool ClearVirtRegs, SlotIndexes *Indexes, LiveIntervals *LIS,
+ LiveRegMatrix *LRM, VirtRegMap *VRM,
+ LiveDebugVariables *DebugVars)
+ : Indexes(Indexes), LIS(LIS), LRM(LRM), VRM(VRM), DebugVars(DebugVars),
+ ClearVirtRegs(ClearVirtRegs) {}
+
+ bool run(MachineFunction &);
+};
+
+class VirtRegRewriterLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ bool ClearVirtRegs;
+ VirtRegRewriterLegacy(bool ClearVirtRegs = true)
+ : MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -243,11 +255,11 @@ class VirtRegRewriter : public MachineFunctionPass {
} // end anonymous namespace
-char VirtRegRewriter::ID = 0;
+char VirtRegRewriterLegacy::ID = 0;
-char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
+char &llvm::VirtRegRewriterID = VirtRegRewriterLegacy::ID;
-INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_BEGIN(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -255,10 +267,10 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
-INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_END(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
-void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
+void VirtRegRewriterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
@@ -276,16 +288,49 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
+bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
+ VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI();
+ LiveDebugVariables &DebugVars =
+ getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ return R.run(MF);
+}
+
+PreservedAnalyses
+VirtRegRewriterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ VirtRegMap &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
+ LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ SlotIndexes &Indexes = MFAM.getResult<SlotIndexesAnalysis>(MF);
+ LiveDebugVariables &DebugVars =
+ MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ if (!R.run(MF))
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ // LiveDebugVariables is preserved by default, so clear it
+ // if this VRegRewriter is the last one in the pipeline.
+ if (ClearVirtRegs)
+ PA.abandon<LiveDebugVariablesAnalysis>();
+ return PA;
+}
+
+bool VirtRegRewriter::run(MachineFunction &fn) {
MF = &fn;
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
- VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
<< "********** Function: " << MF->getName() << '\n');
LLVM_DEBUG(VRM->dump());
@@ -726,6 +771,14 @@ void VirtRegRewriter::rewrite() {
RewriteRegs.clear();
}
+void VirtRegRewriterPass::printPipeline(
+ raw_ostream &OS, function_ref<StringRef(StringRef)>) const {
+ OS << "virt-reg-rewriter<";
+ if (!ClearVirtRegs)
+ OS << "no-";
+ OS << "clear-vregs>";
+}
+
FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
- return new VirtRegRewriter(ClearVirtRegs);
+ return new VirtRegRewriterLegacy(ClearVirtRegs);
}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 191bed1377a94..006612890c072 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1438,6 +1438,19 @@ Expected<bool> parseMachineSinkingPassOptions(StringRef Params) {
"MachineSinkingPass");
}
+Expected<bool> parseVirtRegRewriterPassOptions(StringRef Params) {
+ bool ClearVirtRegs = true;
+ if (!Params.empty()) {
+ ClearVirtRegs = !Params.consume_front("no-");
+ if (Params != "clear-vregs")
+ return make_error<StringError>(
+ formatv("invalid VirtRegRewriter pass parameter '{0}' ", Params)
+ .str(),
+ inconvertibleErrorCode());
+ }
+ return ClearVirtRegs;
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index bdb6d5b51a736..e20c31dd3626f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -2237,7 +2237,7 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// many things rely on the use lists of the physical registers, such as the
// verifier. This is only necessary with allocators which use LiveIntervals,
// since FastRegAlloc does the replacements itself.
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// At this point, the sgpr-regalloc has been done and it is good to have the
// stack slot coloring to try to optimize the SGPR spill stack indices before
@@ -2253,14 +2253,14 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// For allocating other wwm register operands.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::WWM);
addPass(SILowerWWMCopiesPass());
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// TODO: addPass(AMDGPUReserveWWMRegsPass());
// For allocating per-thread VGPRs.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
// TODO: addPreRewrite();
- addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(true));
// TODO: addPass(AMDGPUMarkLastScratchLoadPass());
return Error::success();
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
index c42b570b40812..8ae90bde0c8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
@@ -1,4 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
+
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
# Using the unaligned vector tuples are OK as long as they aren't used
# in a real instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
index 5ef8a94eeaa7c..f9af0a03e51d0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4 -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 %s -o - | FileCheck %s
+# RUN: llc -enable-new-pm -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4 -verify-regalloc -passes="greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>" %s -o - | FileCheck %s
+
# Check that we don't generate *** Bad machine code: Instruction loads
# from dead spill slot ***
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
index 374617c93ce4d..8754547a23a68 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
@@ -2,6 +2,10 @@
# RUN: -start-before=greedy,0 -stop-after=virtregrewriter,0 -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
# RUN: FileCheck %s < %t.yaml
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 \
+# RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>' -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
+# RUN: FileCheck %s < %t.yaml
+
# CHECK: Name: SpillReloadCopies
# CHECK-NEXT: Function: func
# CHECK-NEXT: Args:
diff --git a/llvm/test/CodeGen/X86/pr30821.mir b/llvm/test/CodeGen/X86/pr30821.mir
index 992ef8bbe55f0..dccb49277b519 100644
--- a/llvm/test/CodeGen/X86/pr30821.mir
+++ b/llvm/test/CodeGen/X86/pr30821.mir
@@ -1,4 +1,5 @@
# RUN: llc -x mir < %s -run-pass=greedy,virtregrewriter,stack-slot-coloring | FileCheck %s
+# RUN: llc -x mir < %s -passes=greedy,virt-reg-rewriter,stack-slot-coloring | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
|
|
@llvm/pr-subscribers-backend-x86 Author: Akshat Oke (optimisan) ChangesNot sure why this is squished into VirtRegMap.h Full diff: https://github.com/llvm/llvm-project/pull/130564.diff 12 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index c9e405e1981d9..f5fba0d65401e 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -235,6 +235,21 @@ class VirtRegMapPrinterPass : public PassInfoMixin<VirtRegMapPrinterPass> {
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
+
+class VirtRegRewriterPass : public PassInfoMixin<VirtRegRewriterPass> {
+ bool ClearVirtRegs = true;
+
+public:
+ VirtRegRewriterPass(bool ClearVirtRegs = true)
+ : ClearVirtRegs(ClearVirtRegs) {}
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ static bool isRequired() { return true; }
+
+ void printPipeline(raw_ostream &OS, function_ref<StringRef(StringRef)>) const;
+};
+
} // end llvm namespace
#endif // LLVM_CODEGEN_VIRTREGMAP_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 9afca6c0dab70..b8b0d09b917fb 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -316,7 +316,7 @@ void initializeUnreachableBlockElimLegacyPassPass(PassRegistry &);
void initializeUnreachableMachineBlockElimPass(PassRegistry &);
void initializeVerifierLegacyPassPass(PassRegistry &);
void initializeVirtRegMapWrapperLegacyPass(PassRegistry &);
-void initializeVirtRegRewriterPass(PassRegistry &);
+void initializeVirtRegRewriterLegacyPass(PassRegistry &);
void initializeWasmEHPreparePass(PassRegistry &);
void initializeWinEHPreparePass(PassRegistry &);
void initializeWriteBitcodePassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 9ec9836c15eb5..db227ddaa0e2b 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -81,6 +81,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TwoAddressInstructionPass.h"
#include "llvm/CodeGen/UnreachableBlockElim.h"
+#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/CodeGen/WasmEHPrepare.h"
#include "llvm/CodeGen/WinEHPrepare.h"
#include "llvm/IR/PassManager.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 87253ebc8b789..eab6a6f6cd494 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -215,6 +215,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "virt-reg-rewriter", "VirtRegRewriterPass",
+ [](bool ClearVirtRegs) { return VirtRegRewriterPass(ClearVirtRegs); },
+ parseVirtRegRewriterPassOptions, "no-clear-vregs;clear-vregs")
+
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved from
@@ -287,6 +293,5 @@ DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass)
DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass)
DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass)
DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass)
-DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass)
DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass)
#undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 3169a109aa174..b3ec59889b8b7 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -141,7 +141,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeUnreachableBlockElimLegacyPassPass(Registry);
initializeUnreachableMachineBlockElimPass(Registry);
initializeVirtRegMapWrapperLegacyPass(Registry);
- initializeVirtRegRewriterPass(Registry);
+ initializeVirtRegRewriterLegacyPass(Registry);
initializeWasmEHPreparePass(Registry);
initializeWinEHPreparePass(Registry);
initializeXRayInstrumentationPass(Registry);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0fc3e5d9a3052..a00f6bc0bf3ae 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -197,7 +197,7 @@ VirtRegMap VirtRegMapAnalysis::run(MachineFunction &MF,
//
namespace {
-class VirtRegRewriter : public MachineFunctionPass {
+class VirtRegRewriter {
MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
const TargetInstrInfo *TII = nullptr;
@@ -223,9 +223,21 @@ class VirtRegRewriter : public MachineFunctionPass {
public:
static char ID;
- VirtRegRewriter(bool ClearVirtRegs_ = true) :
- MachineFunctionPass(ID),
- ClearVirtRegs(ClearVirtRegs_) {}
+ VirtRegRewriter(bool ClearVirtRegs, SlotIndexes *Indexes, LiveIntervals *LIS,
+ LiveRegMatrix *LRM, VirtRegMap *VRM,
+ LiveDebugVariables *DebugVars)
+ : Indexes(Indexes), LIS(LIS), LRM(LRM), VRM(VRM), DebugVars(DebugVars),
+ ClearVirtRegs(ClearVirtRegs) {}
+
+ bool run(MachineFunction &);
+};
+
+class VirtRegRewriterLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ bool ClearVirtRegs;
+ VirtRegRewriterLegacy(bool ClearVirtRegs = true)
+ : MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -243,11 +255,11 @@ class VirtRegRewriter : public MachineFunctionPass {
} // end anonymous namespace
-char VirtRegRewriter::ID = 0;
+char VirtRegRewriterLegacy::ID = 0;
-char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
+char &llvm::VirtRegRewriterID = VirtRegRewriterLegacy::ID;
-INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_BEGIN(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -255,10 +267,10 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
-INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_END(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
-void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
+void VirtRegRewriterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
@@ -276,16 +288,49 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
+bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
+ VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI();
+ LiveDebugVariables &DebugVars =
+ getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ return R.run(MF);
+}
+
+PreservedAnalyses
+VirtRegRewriterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ VirtRegMap &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
+ LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ SlotIndexes &Indexes = MFAM.getResult<SlotIndexesAnalysis>(MF);
+ LiveDebugVariables &DebugVars =
+ MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ if (!R.run(MF))
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ // LiveDebugVariables is preserved by default, so clear it
+ // if this VRegRewriter is the last one in the pipeline.
+ if (ClearVirtRegs)
+ PA.abandon<LiveDebugVariablesAnalysis>();
+ return PA;
+}
+
+bool VirtRegRewriter::run(MachineFunction &fn) {
MF = &fn;
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
- VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
<< "********** Function: " << MF->getName() << '\n');
LLVM_DEBUG(VRM->dump());
@@ -726,6 +771,14 @@ void VirtRegRewriter::rewrite() {
RewriteRegs.clear();
}
+void VirtRegRewriterPass::printPipeline(
+ raw_ostream &OS, function_ref<StringRef(StringRef)>) const {
+ OS << "virt-reg-rewriter<";
+ if (!ClearVirtRegs)
+ OS << "no-";
+ OS << "clear-vregs>";
+}
+
FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
- return new VirtRegRewriter(ClearVirtRegs);
+ return new VirtRegRewriterLegacy(ClearVirtRegs);
}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 191bed1377a94..006612890c072 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1438,6 +1438,19 @@ Expected<bool> parseMachineSinkingPassOptions(StringRef Params) {
"MachineSinkingPass");
}
+Expected<bool> parseVirtRegRewriterPassOptions(StringRef Params) {
+ bool ClearVirtRegs = true;
+ if (!Params.empty()) {
+ ClearVirtRegs = !Params.consume_front("no-");
+ if (Params != "clear-vregs")
+ return make_error<StringError>(
+ formatv("invalid VirtRegRewriter pass parameter '{0}' ", Params)
+ .str(),
+ inconvertibleErrorCode());
+ }
+ return ClearVirtRegs;
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index bdb6d5b51a736..e20c31dd3626f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -2237,7 +2237,7 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// many things rely on the use lists of the physical registers, such as the
// verifier. This is only necessary with allocators which use LiveIntervals,
// since FastRegAlloc does the replacements itself.
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// At this point, the sgpr-regalloc has been done and it is good to have the
// stack slot coloring to try to optimize the SGPR spill stack indices before
@@ -2253,14 +2253,14 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// For allocating other wwm register operands.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::WWM);
addPass(SILowerWWMCopiesPass());
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// TODO: addPass(AMDGPUReserveWWMRegsPass());
// For allocating per-thread VGPRs.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
// TODO: addPreRewrite();
- addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(true));
// TODO: addPass(AMDGPUMarkLastScratchLoadPass());
return Error::success();
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
index c42b570b40812..8ae90bde0c8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
@@ -1,4 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
+
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
# Using the unaligned vector tuples are OK as long as they aren't used
# in a real instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
index 5ef8a94eeaa7c..f9af0a03e51d0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4 -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 %s -o - | FileCheck %s
+# RUN: llc -enable-new-pm -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4 -verify-regalloc -passes="greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>" %s -o - | FileCheck %s
+
# Check that we don't generate *** Bad machine code: Instruction loads
# from dead spill slot ***
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
index 374617c93ce4d..8754547a23a68 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
@@ -2,6 +2,10 @@
# RUN: -start-before=greedy,0 -stop-after=virtregrewriter,0 -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
# RUN: FileCheck %s < %t.yaml
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 \
+# RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>' -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
+# RUN: FileCheck %s < %t.yaml
+
# CHECK: Name: SpillReloadCopies
# CHECK-NEXT: Function: func
# CHECK-NEXT: Args:
diff --git a/llvm/test/CodeGen/X86/pr30821.mir b/llvm/test/CodeGen/X86/pr30821.mir
index 992ef8bbe55f0..dccb49277b519 100644
--- a/llvm/test/CodeGen/X86/pr30821.mir
+++ b/llvm/test/CodeGen/X86/pr30821.mir
@@ -1,4 +1,5 @@
# RUN: llc -x mir < %s -run-pass=greedy,virtregrewriter,stack-slot-coloring | FileCheck %s
+# RUN: llc -x mir < %s -passes=greedy,virt-reg-rewriter,stack-slot-coloring | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
|
|
@llvm/pr-subscribers-backend-amdgpu Author: Akshat Oke (optimisan) ChangesNot sure why this is squished into VirtRegMap.h Full diff: https://github.com/llvm/llvm-project/pull/130564.diff 12 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index c9e405e1981d9..f5fba0d65401e 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -235,6 +235,21 @@ class VirtRegMapPrinterPass : public PassInfoMixin<VirtRegMapPrinterPass> {
MachineFunctionAnalysisManager &MFAM);
static bool isRequired() { return true; }
};
+
+class VirtRegRewriterPass : public PassInfoMixin<VirtRegRewriterPass> {
+ bool ClearVirtRegs = true;
+
+public:
+ VirtRegRewriterPass(bool ClearVirtRegs = true)
+ : ClearVirtRegs(ClearVirtRegs) {}
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ static bool isRequired() { return true; }
+
+ void printPipeline(raw_ostream &OS, function_ref<StringRef(StringRef)>) const;
+};
+
} // end llvm namespace
#endif // LLVM_CODEGEN_VIRTREGMAP_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 9afca6c0dab70..b8b0d09b917fb 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -316,7 +316,7 @@ void initializeUnreachableBlockElimLegacyPassPass(PassRegistry &);
void initializeUnreachableMachineBlockElimPass(PassRegistry &);
void initializeVerifierLegacyPassPass(PassRegistry &);
void initializeVirtRegMapWrapperLegacyPass(PassRegistry &);
-void initializeVirtRegRewriterPass(PassRegistry &);
+void initializeVirtRegRewriterLegacyPass(PassRegistry &);
void initializeWasmEHPreparePass(PassRegistry &);
void initializeWinEHPreparePass(PassRegistry &);
void initializeWriteBitcodePassPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 9ec9836c15eb5..db227ddaa0e2b 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -81,6 +81,7 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TwoAddressInstructionPass.h"
#include "llvm/CodeGen/UnreachableBlockElim.h"
+#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/CodeGen/WasmEHPrepare.h"
#include "llvm/CodeGen/WinEHPrepare.h"
#include "llvm/IR/PassManager.h"
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index 87253ebc8b789..eab6a6f6cd494 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -215,6 +215,12 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocGreedyFilterFunc(*PB, Params);
}, "reg-filter"
)
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "virt-reg-rewriter", "VirtRegRewriterPass",
+ [](bool ClearVirtRegs) { return VirtRegRewriterPass(ClearVirtRegs); },
+ parseVirtRegRewriterPassOptions, "no-clear-vregs;clear-vregs")
+
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved from
@@ -287,6 +293,5 @@ DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass)
DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass)
DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass)
DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass)
-DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass)
DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass)
#undef DUMMY_MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 3169a109aa174..b3ec59889b8b7 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -141,7 +141,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeUnreachableBlockElimLegacyPassPass(Registry);
initializeUnreachableMachineBlockElimPass(Registry);
initializeVirtRegMapWrapperLegacyPass(Registry);
- initializeVirtRegRewriterPass(Registry);
+ initializeVirtRegRewriterLegacyPass(Registry);
initializeWasmEHPreparePass(Registry);
initializeWinEHPreparePass(Registry);
initializeXRayInstrumentationPass(Registry);
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 0fc3e5d9a3052..a00f6bc0bf3ae 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -197,7 +197,7 @@ VirtRegMap VirtRegMapAnalysis::run(MachineFunction &MF,
//
namespace {
-class VirtRegRewriter : public MachineFunctionPass {
+class VirtRegRewriter {
MachineFunction *MF = nullptr;
const TargetRegisterInfo *TRI = nullptr;
const TargetInstrInfo *TII = nullptr;
@@ -223,9 +223,21 @@ class VirtRegRewriter : public MachineFunctionPass {
public:
static char ID;
- VirtRegRewriter(bool ClearVirtRegs_ = true) :
- MachineFunctionPass(ID),
- ClearVirtRegs(ClearVirtRegs_) {}
+ VirtRegRewriter(bool ClearVirtRegs, SlotIndexes *Indexes, LiveIntervals *LIS,
+ LiveRegMatrix *LRM, VirtRegMap *VRM,
+ LiveDebugVariables *DebugVars)
+ : Indexes(Indexes), LIS(LIS), LRM(LRM), VRM(VRM), DebugVars(DebugVars),
+ ClearVirtRegs(ClearVirtRegs) {}
+
+ bool run(MachineFunction &);
+};
+
+class VirtRegRewriterLegacy : public MachineFunctionPass {
+public:
+ static char ID;
+ bool ClearVirtRegs;
+ VirtRegRewriterLegacy(bool ClearVirtRegs = true)
+ : MachineFunctionPass(ID), ClearVirtRegs(ClearVirtRegs) {}
void getAnalysisUsage(AnalysisUsage &AU) const override;
@@ -243,11 +255,11 @@ class VirtRegRewriter : public MachineFunctionPass {
} // end anonymous namespace
-char VirtRegRewriter::ID = 0;
+char VirtRegRewriterLegacy::ID = 0;
-char &llvm::VirtRegRewriterID = VirtRegRewriter::ID;
+char &llvm::VirtRegRewriterID = VirtRegRewriterLegacy::ID;
-INITIALIZE_PASS_BEGIN(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_BEGIN(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -255,10 +267,10 @@ INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveRegMatrixWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(LiveStacksWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(VirtRegMapWrapperLegacy)
-INITIALIZE_PASS_END(VirtRegRewriter, "virtregrewriter",
+INITIALIZE_PASS_END(VirtRegRewriterLegacy, "virtregrewriter",
"Virtual Register Rewriter", false, false)
-void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
+void VirtRegRewriterLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<LiveIntervalsWrapperPass>();
AU.addPreserved<LiveIntervalsWrapperPass>();
@@ -276,16 +288,49 @@ void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
MachineFunctionPass::getAnalysisUsage(AU);
}
-bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
+bool VirtRegRewriterLegacy::runOnMachineFunction(MachineFunction &MF) {
+ VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI();
+ LiveDebugVariables &DebugVars =
+ getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ return R.run(MF);
+}
+
+PreservedAnalyses
+VirtRegRewriterPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ VirtRegMap &VRM = MFAM.getResult<VirtRegMapAnalysis>(MF);
+ LiveIntervals &LIS = MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ LiveRegMatrix &LRM = MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ SlotIndexes &Indexes = MFAM.getResult<SlotIndexesAnalysis>(MF);
+ LiveDebugVariables &DebugVars =
+ MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+
+ VirtRegRewriter R(ClearVirtRegs, &Indexes, &LIS, &LRM, &VRM, &DebugVars);
+ if (!R.run(MF))
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ // LiveDebugVariables is preserved by default, so clear it
+ // if this VRegRewriter is the last one in the pipeline.
+ if (ClearVirtRegs)
+ PA.abandon<LiveDebugVariablesAnalysis>();
+ return PA;
+}
+
+bool VirtRegRewriter::run(MachineFunction &fn) {
MF = &fn;
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
MRI = &MF->getRegInfo();
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
- LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
- VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+
LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
<< "********** Function: " << MF->getName() << '\n');
LLVM_DEBUG(VRM->dump());
@@ -726,6 +771,14 @@ void VirtRegRewriter::rewrite() {
RewriteRegs.clear();
}
+void VirtRegRewriterPass::printPipeline(
+ raw_ostream &OS, function_ref<StringRef(StringRef)>) const {
+ OS << "virt-reg-rewriter<";
+ if (!ClearVirtRegs)
+ OS << "no-";
+ OS << "clear-vregs>";
+}
+
FunctionPass *llvm::createVirtRegRewriter(bool ClearVirtRegs) {
- return new VirtRegRewriter(ClearVirtRegs);
+ return new VirtRegRewriterLegacy(ClearVirtRegs);
}
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 191bed1377a94..006612890c072 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1438,6 +1438,19 @@ Expected<bool> parseMachineSinkingPassOptions(StringRef Params) {
"MachineSinkingPass");
}
+Expected<bool> parseVirtRegRewriterPassOptions(StringRef Params) {
+ bool ClearVirtRegs = true;
+ if (!Params.empty()) {
+ ClearVirtRegs = !Params.consume_front("no-");
+ if (Params != "clear-vregs")
+ return make_error<StringError>(
+ formatv("invalid VirtRegRewriter pass parameter '{0}' ", Params)
+ .str(),
+ inconvertibleErrorCode());
+ }
+ return ClearVirtRegs;
+}
+
} // namespace
/// Tests whether a pass name starts with a valid prefix for a default pipeline
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index bdb6d5b51a736..e20c31dd3626f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -2237,7 +2237,7 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// many things rely on the use lists of the physical registers, such as the
// verifier. This is only necessary with allocators which use LiveIntervals,
// since FastRegAlloc does the replacements itself.
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// At this point, the sgpr-regalloc has been done and it is good to have the
// stack slot coloring to try to optimize the SGPR spill stack indices before
@@ -2253,14 +2253,14 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignmentOptimized(
// For allocating other wwm register operands.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::WWM);
addPass(SILowerWWMCopiesPass());
- // TODO: addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(false));
// TODO: addPass(AMDGPUReserveWWMRegsPass());
// For allocating per-thread VGPRs.
addRegAlloc<RAGreedyPass>(addPass, RegAllocPhase::VGPR);
// TODO: addPreRewrite();
- addPass(VirtRegRewriterPass(false));
+ addPass(VirtRegRewriterPass(true));
// TODO: addPass(AMDGPUMarkLastScratchLoadPass());
return Error::success();
diff --git a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
index c42b570b40812..8ae90bde0c8ce 100644
--- a/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
+++ b/llvm/test/CodeGen/AMDGPU/alloc-aligned-tuples-gfx90a.mir
@@ -1,4 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
+
+# RUN: llc -enable-new-pm -mtriple=amdgcn -mcpu=gfx90a -start-before=greedy,0 -stop-after=virtregrewriter,2 -verify-machineinstrs -o - %s | FileCheck --check-prefixes=GCN,GFX90A %s
# Using the unaligned vector tuples are OK as long as they aren't used
# in a real instruction.
diff --git a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
index 5ef8a94eeaa7c..f9af0a03e51d0 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir
@@ -1,6 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4 -verify-regalloc -start-before=greedy,0 -stop-after=virtregrewriter,0 %s -o - | FileCheck %s
+# RUN: llc -enable-new-pm -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -stress-regalloc=4 -verify-regalloc -passes="greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>" %s -o - | FileCheck %s
+
# Check that we don't generate *** Bad machine code: Instruction loads
# from dead spill slot ***
diff --git a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
index 374617c93ce4d..8754547a23a68 100644
--- a/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
+++ b/llvm/test/CodeGen/AMDGPU/greedy-remark-crash-unassigned-reg.mir
@@ -2,6 +2,10 @@
# RUN: -start-before=greedy,0 -stop-after=virtregrewriter,0 -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
# RUN: FileCheck %s < %t.yaml
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 \
+# RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>' -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s
+# RUN: FileCheck %s < %t.yaml
+
# CHECK: Name: SpillReloadCopies
# CHECK-NEXT: Function: func
# CHECK-NEXT: Args:
diff --git a/llvm/test/CodeGen/X86/pr30821.mir b/llvm/test/CodeGen/X86/pr30821.mir
index 992ef8bbe55f0..dccb49277b519 100644
--- a/llvm/test/CodeGen/X86/pr30821.mir
+++ b/llvm/test/CodeGen/X86/pr30821.mir
@@ -1,4 +1,5 @@
# RUN: llc -x mir < %s -run-pass=greedy,virtregrewriter,stack-slot-coloring | FileCheck %s
+# RUN: llc -x mir < %s -passes=greedy,virt-reg-rewriter,stack-slot-coloring | FileCheck %s
--- |
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
|
arsenm
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| @@ -2,6 +2,10 @@ | |||
| # RUN: -start-before=greedy,0 -stop-after=virtregrewriter,0 -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s | |||
| # RUN: FileCheck %s < %t.yaml | |||
|
|
|||
| # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 \ | |||
| # RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>' -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s | |||
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Suggested change
| # RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>' -pass-remarks='.*' -pass-remarks-output=%t.yaml -o /dev/null %s | |
| # RUN: -passes='greedy<sgpr>,virt-reg-rewriter<no-clear-vregs>' -pass-remarks='.*' -pass-remarks-output=%t.yaml -filetype=null %s |
Not sure why this is squished into VirtRegMap.h
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|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/51/builds/15293 Here is the relevant piece of the build log for the reference |
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Apr 30, 2025
| @@ -1502,6 +1502,19 @@ Expected<bool> parseMachineBlockPlacementPassOptions(StringRef Params) { | |||
| inconvertibleErrorCode()); | |||
| } | |||
| return AllowTailMerge; | |||
| }; | |||
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extra semicolon here causes a build failure
| @@ -223,9 +223,21 @@ class VirtRegRewriter : public MachineFunctionPass { | |||
|
|
|||
| public: | |||
| static char ID; | |||
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unused ID here causes a build failure
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Not sure why this is squished into VirtRegMap.h