[GISel][RISCV] Legalize `G_FREM` to use fmod #93063

dtcxzyw · 2024-05-22T16:14:52Z

This patch adds support for G_FREM on RISCV.

Unfortunately, I cannot provide vector tests for scalarize and half/bfloat16 tests for minScalar.

llvmbot · 2024-05-22T16:15:28Z

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-risc-v

Author: Yingwei Zheng (dtcxzyw)

Changes

This patch adds support for G_FREM on RISCV.

Unfortunately, I cannot provide vector tests for scalarize and half/bfloat16 tests for minScalar.

Full diff: https://github.com/llvm/llvm-project/pull/93063.diff

4 Files Affected:

(modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+5)
(added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir (+66)
(added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir (+57)
(added) llvm/test/CodeGen/RISCV/GlobalISel/libcalls.ll (+51)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index a1d3aadb816ab..8cc826c274993 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -372,6 +372,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
                                G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM})
       .legalIf(typeIsScalarFPArith(0, ST));
 
+  getActionDefinitionsBuilder(G_FREM)
+      .libcallFor({s32, s64})
+      .minScalar(0, s32)
+      .scalarize(0);
+
   getActionDefinitionsBuilder(G_FCOPYSIGN)
       .legalIf(all(typeIsScalarFPArith(0, ST), typeIsScalarFPArith(1, ST)));
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir
new file mode 100644
index 0000000000000..447b3a320649d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir
@@ -0,0 +1,66 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - | FileCheck %s
+---
+name:            test_f32
+body:             |
+  bb.1.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: test_f32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+    ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
+    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+    ; CHECK-NEXT: $x10 = COPY [[COPY2]](s32)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(s32) = COPY $x10
+    %1:_(s32) = COPY $x11
+    %2:_(s32) = G_FREM %0, %1
+    $x10 = COPY %2(s32)
+    PseudoRET implicit $x10
+
+...
+---
+name:            test_f64
+body:             |
+  bb.1.entry:
+    liveins: $x10, $x11, $x12, $x13
+
+    ; CHECK-LABEL: name: test_f64
+    ; CHECK: liveins: $x10, $x11, $x12, $x13
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
+    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
+    ; CHECK-NEXT: $x11 = COPY [[COPY1]](s32)
+    ; CHECK-NEXT: $x12 = COPY [[COPY2]](s32)
+    ; CHECK-NEXT: $x13 = COPY [[COPY3]](s32)
+    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmod, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit-def $x10, implicit-def $x11
+    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x10
+    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x11
+    ; CHECK-NEXT: $x10 = COPY [[COPY4]](s32)
+    ; CHECK-NEXT: $x11 = COPY [[COPY5]](s32)
+    ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+    %2:_(s32) = COPY $x10
+    %3:_(s32) = COPY $x11
+    %0:_(s64) = G_MERGE_VALUES %2(s32), %3(s32)
+    %4:_(s32) = COPY $x12
+    %5:_(s32) = COPY $x13
+    %1:_(s64) = G_MERGE_VALUES %4(s32), %5(s32)
+    %6:_(s64) = G_FREM %0, %1
+    %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
+    $x10 = COPY %7(s32)
+    $x11 = COPY %8(s32)
+    PseudoRET implicit $x10, implicit $x11
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir
new file mode 100644
index 0000000000000..5a6b3b7667375
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv64.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - | FileCheck %s
+---
+name:            test_f32
+body:             |
+  bb.1.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: test_f32
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+    ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
+    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmodf, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
+    ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %2:_(s64) = COPY $x10
+    %0:_(s32) = G_TRUNC %2(s64)
+    %3:_(s64) = COPY $x11
+    %1:_(s32) = G_TRUNC %3(s64)
+    %4:_(s32) = G_FREM %0, %1
+    %5:_(s64) = G_ANYEXT %4(s32)
+    $x10 = COPY %5(s64)
+    PseudoRET implicit $x10
+
+...
+---
+name:            test_f64
+body:             |
+  bb.1.entry:
+    liveins: $x10, $x11
+
+    ; CHECK-LABEL: name: test_f64
+    ; CHECK: liveins: $x10, $x11
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+    ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
+    ; CHECK-NEXT: $x11 = COPY [[COPY1]](s64)
+    ; CHECK-NEXT: PseudoCALL target-flags(riscv-call) &fmod, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit $x11, implicit-def $x10
+    ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x10
+    ; CHECK-NEXT: $x10 = COPY [[COPY2]](s64)
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:_(s64) = COPY $x10
+    %1:_(s64) = COPY $x11
+    %2:_(s64) = G_FREM %0, %1
+    $x10 = COPY %2(s64)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/libcalls.ll b/llvm/test/CodeGen/RISCV/GlobalISel/libcalls.ll
new file mode 100644
index 0000000000000..aaef8d98c812d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/libcalls.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv32 -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -global-isel -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64
+
+define float @test_f32(float %x, float %y) nounwind {
+; RV32-LABEL: test_f32:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT:    call fmodf
+; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_f32:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi sp, sp, -16
+; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT:    call fmodf
+; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    ret
+entry:
+  %z = frem float %x, %y
+  ret float %z
+}
+
+define double @test_f64(double %x, double %y) nounwind {
+; RV32-LABEL: test_f64:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT:    call fmod
+; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: test_f64:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    addi sp, sp, -16
+; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64-NEXT:    call fmod
+; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    ret
+entry:
+  %z = frem double %x, %y
+  ret double %z
+}

topperc

LGTM<

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

arsenm

It should be possible to test the scalarize case

llvm/test/CodeGen/RISCV/GlobalISel/libcalls.ll

dtcxzyw · 2024-05-23T12:41:00Z

It should be possible to test the scalarize case

I tried the following 4 variants, but no one works :(

; unable to legalize instruction: %3:_(<2 x s32>) = G_LOAD %1:_(p0) :: (load (<2 x s32>) from %ir.py)
define void @test_v2f32(ptr %px, ptr %py) nounwind {
entry:
  %x = load <2 x float>, ptr %px
  %y = load <2 x float>, ptr %py
  %1 = frem <2 x float> %x, %y
  store <2 x float> %1, ptr %px
  ret void
}

; unable to lower arguments: ptr
define <2 x float> @test_v2f32(<2 x float> %x, <2 x float> %y) nounwind {
entry:
  %1 = frem <2 x float> %x, %y
  ret <2 x float> %1
}

; unable to translate instruction: frem
define void @test_nxv2f32(ptr %px, ptr %py) nounwind {
entry:
  %x = load <vscale x 2 x float>, ptr %px
  %y = load <vscale x 2 x float>, ptr %py
  %1 = frem <vscale x 2 x float> %x, %y
  store <vscale x 2 x float> %1, ptr %px
  ret void
}

; unable to translate instruction: frem
define <vscale x 2 x float> @test_nxv2f32(<vscale x 2 x float> %x, <vscale x 2 x float> %y) nounwind {
entry:
  %1 = frem <vscale x 2 x float> %x, %y
  ret <vscale x 2 x float> %1
}

arsenm · 2024-05-23T12:42:18Z

It should be possible to test the scalarize case

I tried the following 4 variants, but no one works :(

This is the case where MIR tests are useful because you don't have to bring up all the other parts

dtcxzyw · 2024-05-23T12:55:21Z

It should be possible to test the scalarize case

I tried the following 4 variants, but no one works :(

This is the case where MIR tests are useful because you don't have to bring up all the other parts

These MIR tests don't work:

---
name:            frem_v2f32
body:             |
  bb.0.entry:
    ; unable to legalize instruction: %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %0:_(<2 x s32>)
    %0:_(<2 x s32>) = COPY $v8
    %1:_(<2 x s32>) = COPY $v9
    %2:_(<2 x s32>) = G_FREM %0, %1
    $v8 = COPY %2(<2 x s32>)
    PseudoRET implicit $v8

...
---
name:            frem_nxv2f32
body:             |
  bb.0.entry:
    ; Invalid size request on a scalable vector.
    %0:_(<vscale x 2 x s32>) = COPY $v8
    %1:_(<vscale x 2 x s32>) = COPY $v9
    %2:_(<vscale x 2 x s32>) = G_FREM %0, %1
    $v8 = COPY %2(<vscale x 2 x s32>)
    PseudoRET implicit $v8

...

arsenm · 2024-05-23T13:18:58Z

It should be possible to test the scalarize case

I tried the following 4 variants, but no one works :(

This is the case where MIR tests are useful because you don't have to bring up all the other parts

These MIR tests don't work:
---
name:            frem_v2f32
body:             |
  bb.0.entry:
    ; unable to legalize instruction: %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %0:_(<2 x s32>)

If you use -global-isel-abort=0 or 2, you can check the partially legalized output

dtcxzyw · 2024-05-23T13:51:43Z

It should be possible to test the scalarize case

I tried the following 4 variants, but no one works :(

This is the case where MIR tests are useful because you don't have to bring up all the other parts

These MIR tests don't work:
---
name:            frem_v2f32
body:             |
  bb.0.entry:
    ; unable to legalize instruction: %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %0:_(<2 x s32>)
If you use -global-isel-abort=0 or 2, you can check the partially legalized output

Done. Thank you!

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir

[GISel][RISCV] Legalize G_FREM to use fmod

b1c31b2

dtcxzyw requested review from arsenm, michaelmaitland, tschuett and topperc May 22, 2024 16:14

llvmbot added backend:RISC-V llvm:globalisel labels May 22, 2024

topperc approved these changes May 22, 2024

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michaelmaitland requested changes May 22, 2024

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llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp Show resolved Hide resolved

arsenm reviewed May 22, 2024

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arsenm reviewed May 23, 2024

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llvm/test/CodeGen/RISCV/GlobalISel/libcalls.ll Show resolved Hide resolved

[GISel][RISCV] Add todo.

b2a39a5

[GISel][RISCV] Add half/vector support.

bd1c51e

arsenm reviewed May 23, 2024

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llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-frem-rv32.mir Outdated Show resolved Hide resolved

[GISel][RISCV] Rename tests. NFC.

804b955

arsenm approved these changes May 23, 2024

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dtcxzyw merged commit 558cb29 into llvm:main May 23, 2024
3 checks passed

dtcxzyw deleted the gisel-frem branch May 23, 2024 16:34

dtcxzyw mentioned this pull request May 29, 2024

[GISel] Legalize bitreverse with types smaller than 8 bits #92998

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