[AMDGPU] Add tests for SIPreAllocateWWMRegs #109963

optimisan · 2024-09-25T11:25:34Z

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optimisan · 2024-09-25T11:25:52Z

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llvmbot · 2024-09-25T11:35:44Z

@llvm/pr-subscribers-backend-amdgpu

Author: Akshat Oke (Akshat-Oke)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/109963.diff

2 Files Affected:

(added) llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir (+26)
(added) llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir (+21)

diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
new file mode 100644
index 00000000000000..f2db299f575f5e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s  | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_regs_strict
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr1
+    ; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
+    ; CHECK: liveins: $sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+    ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
+    ; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0, implicit $exec
+    ; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+    %0:vgpr_32 = IMPLICIT_DEF
+    renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+    %24:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %25:vgpr_32 = V_MOV_B32_dpp %24:vgpr_32(tied-def 0), %0:vgpr_32, 323, 12, 15, 0, implicit $exec
+    $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
+    %2:vgpr_32 = COPY %0:vgpr_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
new file mode 100644
index 00000000000000..f0efe74878d831
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir
@@ -0,0 +1,21 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s
+
+---
+
+name: pre_allocate_wwm_spill_to_vgpr
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr1
+    ; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
+    ; CHECK: liveins: $sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+    %0:vgpr_32 = IMPLICIT_DEF
+    %23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32
+    %2:vgpr_32 = COPY %0:vgpr_32
+...
+

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir

arsenm · 2024-09-25T12:02:46Z

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir

+    ; CHECK-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
+    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+    %0:vgpr_32 = IMPLICIT_DEF
+    %23:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0:vgpr_32


Compact register numbers

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-sgpr-spills.mir

arsenm · 2024-10-07T12:04:20Z

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir

+    ; CHECK2-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
+    %0:vgpr_32 = IMPLICIT_DEF
+    %1:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0
+    %2:vgpr_32 = COPY %0


Missing ... at end of function

arsenm · 2024-10-14T05:50:38Z

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir

+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s  | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2


Move the -mcpu together with -mtriple

arsenm · 2024-10-14T05:51:00Z

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir

+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s  | FileCheck %s
+# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2
+
+---


Add fixme to check the MachineFunctionInfo reserved register information

Is it for WWM reserved registers?

But we have that already(?)

wwmReservedRegs: - '$vgpr0'

Then you need to write manual checks for it. Update_mir_test_checks doesn't currently support the function level properties

Added a comment for the manual check.

arsenm · 2024-10-14T12:21:29Z

llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir

@@ -0,0 +1,49 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5


Best to remote this and remove the comment then

What is remote?

optimisan · 2024-10-22T09:41:00Z

Merge activity

Oct 22, 5:41 AM EDT: A user started a stack merge that includes this pull request via Graphite.
Oct 22, 6:00 AM EDT: Graphite rebased this pull request as part of a merge.
Oct 22, 6:01 AM EDT: Graphite rebased this pull request as part of a merge.
Oct 22, 6:03 AM EDT: A user merged this pull request with Graphite.

This was referenced Sep 25, 2024

[NewPM][CodeGen] Port VirtRegMap to NPM #109936

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[NewPM][CodeGen] Port LiveRegMatrix to NPM #109938

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optimisan mentioned this pull request Sep 25, 2024

[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM #109939

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optimisan requested a review from cdevadas September 25, 2024 11:34

optimisan marked this pull request as ready for review September 25, 2024 11:35

llvmbot added the backend:AMDGPU label Sep 25, 2024

arsenm reviewed Sep 25, 2024

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optimisan force-pushed the users/Akshat-Oke/port-lrm branch from 22bb8f0 to f2687b0 Compare October 7, 2024 10:28

optimisan force-pushed the users/Akshat-Oke/09-25-_amdgpu_add_tests_for_sipreallocatewwmregs branch from 3d87209 to 8da3a2c Compare October 7, 2024 10:28

optimisan mentioned this pull request Oct 7, 2024

[CodeGen] LiveIntervalUnions::Array Implement move constructor #111357

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optimisan force-pushed the users/Akshat-Oke/09-25-_amdgpu_add_tests_for_sipreallocatewwmregs branch from 8da3a2c to 131cedb Compare October 8, 2024 04:46

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optimisan force-pushed the users/Akshat-Oke/09-25-_amdgpu_add_tests_for_sipreallocatewwmregs branch from 131cedb to 9bddae3 Compare October 14, 2024 05:44

arsenm approved these changes Oct 14, 2024

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optimisan force-pushed the users/Akshat-Oke/09-25-_amdgpu_add_tests_for_sipreallocatewwmregs branch from 604653e to 43c0d2c Compare October 14, 2024 13:35

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Base automatically changed from users/Akshat-Oke/port-lrm to main October 22, 2024 09:58

optimisan added 2 commits October 22, 2024 10:00

[AMDGPU] Add tests for SIPreAllocateWWMRegs

c789547

Keep tests in one file

6169a44

optimisan force-pushed the users/Akshat-Oke/09-25-_amdgpu_add_tests_for_sipreallocatewwmregs branch 2 times, most recently from af68ad6 to 6169a44 Compare October 22, 2024 10:00

optimisan merged commit f8cb526 into main Oct 22, 2024
5 of 6 checks passed

optimisan deleted the users/Akshat-Oke/09-25-_amdgpu_add_tests_for_sipreallocatewwmregs branch October 22, 2024 10:03

		# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s \| FileCheck %s
		# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s \| FileCheck %s --check-prefix=CHECK2

		@@ -0,0 +1,49 @@
		# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5

[AMDGPU] Add tests for SIPreAllocateWWMRegs #109963

[AMDGPU] Add tests for SIPreAllocateWWMRegs #109963

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optimisan commented Sep 25, 2024 •

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