AMDGPU: Use generated checks in unchecked test

[arsenm]

Also replace undef uses

[arsenm]

• AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks #131317
• AMDGPU: Switch scheduler-subrange-crash.ll to generated checks #131316
• AMDGPU: Switch test to generated checks #131315
• AMDGPU: Migrate more tests away from undef #131314
• AMDGPU: Migrate some tests away from undef #131277
• AMDGPU: Use generated checks in coalescer_distribute.ll #131276
• AMDGPU: Use generated checks in unchecked test #131275 👈 (View in Graphite)
• AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test #131259
• AMDGPU: Add generated checks to compile only test #131258
• AMDGPU: Switch a test to generated checks which only tested labels #131257
• AMDGPU: Remove undef in subreg-coalescer-crash.ll #131256
• AMDGPU: Switch a test with only function label checks to generated #131255
• AMDGPU: Replace undef references with poison in some MIR tests #131254
• AMDGPU: Use generated checks in test missing checks #131110
• AMDGPU: Replace some test undef uses with poison #131103
• AMDGPU: Replace more undef test pointer uses with poison #131102
• AMDGPU: Replace test uses of ptr addrspace(5) undef with poison #131101
• AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests #131095
• AMDGPU: Replace some test i32 undef uses with poison #131092 : 1 other dependent PR (#131106 )
• AMDGPU: Replace some float undef test uses with poison #131090
• AMDGPU: Replace i16 undefs with poison in tests #131084
• AMDGPU: Replace half undef uses with poison in tests #131083
• main

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[llvmbot]

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Also replace undef uses

---

Full diff: https://github.com/llvm/llvm-project/pull/131275.diff

1 Files Affected:

• (modified) llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll (+21-4)

diff --git a/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll b/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
index 1daba85ae0122..bb0b661e800c3 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
@@ -1,4 +1,5 @@
-; RUN: llc -mtriple=amdgcn < %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn < %s | FileCheck %s
 
 ; Tests for a bug in SelectionDAG::UpdateNodeOperands exposed by VectorLegalizer
 ; where divergence information is not updated.
@@ -6,21 +7,37 @@
 declare i32 @llvm.amdgcn.workitem.id.x()
 
 define amdgpu_kernel void @spam(ptr addrspace(1) noalias %arg) {
+; CHECK-LABEL: spam:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
+; CHECK-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    s_mov_b32 s3, 0xf000
+; CHECK-NEXT:    s_mov_b32 s2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0x7ff80000
+; CHECK-NEXT:    v_mov_b32_e32 v0, v5
+; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
+; CHECK-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr64 offset:16
+; CHECK-NEXT:    s_waitcnt expcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v2, v5
+; CHECK-NEXT:    v_mov_b32_e32 v3, v5
+; CHECK-NEXT:    buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 addr64 offset:48
+; CHECK-NEXT:    s_endpgm
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = zext i32 %tmp to i64
   %tmp2 = getelementptr inbounds double, ptr addrspace(1) %arg, i64 %tmp1
   %tmp3 = load double, ptr addrspace(1) %tmp2, align 8
-  %tmp4 = fadd double undef, 0.000000e+00
+  %tmp4 = fadd double 0x7FF8000000000000, 0.000000e+00
   %tmp5 = insertelement <2 x double> poison, double %tmp4, i64 0
   %tmp6 = insertelement <2 x double> %tmp5, double %tmp3, i64 1
   %tmp7 = insertelement <2 x double> %tmp6, double 0.000000e+00, i64 1
-  %tmp8 = fadd <2 x double> zeroinitializer, undef
+  %tmp8 = fadd <2 x double> zeroinitializer, splat (double 0x7FF8000000000000)
   %tmp9 = fadd <2 x double> %tmp7, zeroinitializer
   %tmp10 = extractelement <2 x double> %tmp8, i64 0
   %tmp11 = getelementptr inbounds double, ptr addrspace(1) %tmp2, i64 2
   store double %tmp10, ptr addrspace(1) %tmp11, align 8
   %tmp12 = getelementptr inbounds double, ptr addrspace(1) %tmp2, i64 3
-  store double undef, ptr addrspace(1) %tmp12, align 8
+  store double poison, ptr addrspace(1) %tmp12, align 8
   %tmp13 = extractelement <2 x double> %tmp9, i64 0
   %tmp14 = getelementptr inbounds double, ptr addrspace(1) %tmp2, i64 6
   store double %tmp13, ptr addrspace(1) %tmp14, align 8

[arsenm]

Merge activity

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