AMDGPU: Switch a test to generated checks which only tested labels

[arsenm]

Also remove an undef use

[arsenm]

• AMDGPU: Switch simplifydemandedbits-recursion.ll to generated checks #131317
• AMDGPU: Switch scheduler-subrange-crash.ll to generated checks #131316
• AMDGPU: Switch test to generated checks #131315
• AMDGPU: Migrate more tests away from undef #131314
• AMDGPU: Migrate some tests away from undef #131277
• AMDGPU: Use generated checks in coalescer_distribute.ll #131276
• AMDGPU: Use generated checks in unchecked test #131275
• AMDGPU: Use generated tests in reg-coalescer-sched-crash.ll test #131259
• AMDGPU: Add generated checks to compile only test #131258
• AMDGPU: Switch a test to generated checks which only tested labels #131257 👈 (View in Graphite)
• AMDGPU: Remove undef in subreg-coalescer-crash.ll #131256
• AMDGPU: Switch a test with only function label checks to generated #131255
• AMDGPU: Replace undef references with poison in some MIR tests #131254
• AMDGPU: Use generated checks in test missing checks #131110
• AMDGPU: Replace some test undef uses with poison #131103
• AMDGPU: Replace more undef test pointer uses with poison #131102
• AMDGPU: Replace test uses of ptr addrspace(5) undef with poison #131101
• AMDGPU: Replace ptr addrspace(4) undef uses with poison in tests #131095
• AMDGPU: Replace some test i32 undef uses with poison #131092 : 1 other dependent PR (#131106 )
• AMDGPU: Replace some float undef test uses with poison #131090
• AMDGPU: Replace i16 undefs with poison in tests #131084
• AMDGPU: Replace half undef uses with poison in tests #131083
• main

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[llvmbot]

@llvm/pr-subscribers-llvm-globalisel

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

Also remove an undef use

---

Full diff: https://github.com/llvm/llvm-project/pull/131257.diff

1 Files Affected:

• (modified) llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll (+47-6)

diff --git a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
index d198ec28f1602..21d4bcfcdc8c1 100644
--- a/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
+++ b/llvm/test/CodeGen/AMDGPU/bug-vopc-commute.ll
@@ -1,16 +1,58 @@
-; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=verde < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
 
-; CHECK-LABEL: {{^}}main:
-;
 ; Test for compilation only. This generated an invalid machine instruction
 ; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both
 ; of which were in SGPRs.
 define amdgpu_vs float @main(i32 %v) {
+; GFX6-LABEL: main:
+; GFX6:       ; %bb.0: ; %main_body
+; GFX6-NEXT:    s_cbranch_scc1 .LBB0_2
+; GFX6-NEXT:  ; %bb.1: ; %IF57
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX6-NEXT:    s_buffer_load_dword s0, s[0:3], 0xf0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:    s_cbranch_scc1 .LBB0_4
+; GFX6-NEXT:  ; %bb.3: ; %IF60
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX6-NEXT:    s_buffer_load_dword s0, s[0:3], 0xf4
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX6-NEXT:    s_cbranch_scc0 .LBB0_6
+; GFX6-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX6-NEXT:    s_branch .LBB0_7
+; GFX6-NEXT:  .LBB0_6: ; %IF63
+; GFX6-NEXT:  .LBB0_7:
+;
+; GFX8-LABEL: main:
+; GFX8:       ; %bb.0: ; %main_body
+; GFX8-NEXT:    s_cbranch_scc1 .LBB0_2
+; GFX8-NEXT:  ; %bb.1: ; %IF57
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_2: ; %ENDIF56
+; GFX8-NEXT:    s_buffer_load_dword s0, s[0:3], 0x3c0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:    s_cbranch_scc1 .LBB0_4
+; GFX8-NEXT:  ; %bb.3: ; %IF60
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:  .LBB0_4: ; %ENDIF59
+; GFX8-NEXT:    s_buffer_load_dword s0, s[0:3], 0x3d0
+; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX8-NEXT:    s_cmp_eq_u32 s0, 0
+; GFX8-NEXT:    s_cbranch_scc0 .LBB0_6
+; GFX8-NEXT:  ; %bb.5: ; %ENDIF62
+; GFX8-NEXT:    s_branch .LBB0_7
+; GFX8-NEXT:  .LBB0_6: ; %IF63
+; GFX8-NEXT:  .LBB0_7:
 main_body:
   %d1 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 960, i32 0)
   %d2 = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> poison, i32 976, i32 0)
-  br i1 undef, label %ENDIF56, label %IF57
+  br i1 poison, label %ENDIF56, label %IF57
 
 IF57:                                             ; preds = %ENDIF
   %v.1 = mul i32 %v, 2
@@ -40,7 +82,6 @@ ENDIF62:                                          ; preds = %ENDIF59
   ret float %r
 }
 
-; Function Attrs: nounwind readnone
 declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #0
 
 attributes #0 = { nounwind readnone }

[arsenm]

Merge activity

• Mar 14, 3:38 AM EDT: A user started a stack merge that includes this pull request via Graphite.
• Mar 14, 3:52 AM EDT: Graphite rebased this pull request as part of a merge.
• Mar 14, 3:54 AM EDT: A user merged this pull request with Graphite.